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參數(shù)資料
| 型號： | DS2423X |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4kbit 1-Wire RAM with Counter |
| 中文描述： | 4kbit的1 - Wire與反內(nèi)存 |
| 文件頁數(shù)： | 25/25頁 |
| 文件大小： | 331K |
| 代理商： | DS2423X |
DS2423
25 of 25
NOTES:
1)
All voltages are referenced to ground.
2)
V
PUP
= external pullup voltage.
3)
Input load is to ground.
4)
An additional reset or communication sequence cannot begin until the reset high time has expired.
5)
Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1μs of this falling edge.
6)
Capacitance on the data pin could be 800pF when power is first applied. If a 5k
resistor is used to
pull up the data line to V
PUP
, 5μs after power has been applied the parasite capacitance will not affect
normal communications.
7)
The reset low time (t
RSTL
) should be restricted to a maximum of 960μs, to allow interrupt signaling,
otherwise, it could mask or conceal interrupt pulses.
8)
V
IH
is a function of the external pullup resistor and V
PUP
.
9)
Under certain low voltage conditions V
ILMAX
may have to be reduced to as much as 0.5V to always
guarantee a Presence Pulse.
10)
The counter inputs are designed for interfacing to mechanical switches and piezo sensors. If
interfacing to digital circuits, one should use an open drain driver.
11)
A lower impedance pullup, e. g., for reed switches, can be achieved by connecting an external resistor
from the counter input to V
BAT
.
12)
Read and write scratchpad (all 32 bytes) at V
BAT
of 3.0 V.
13)
Each low-going edge on a counter input resets the channel’s debounce timer. The debounce time
starts as the input voltage rises beyond the trip point. In order for the next pulse to be counted the
debounce time must have expired.
14)
The optimal sampling point for the master is as close as possible to the end time of the t
RDV
period
without exceeding t
RDV
. For the case of a Read-One Time slot, this maximizes the amount of time for
the pullup resistor to recover to a high level. For a Read-Zero Time slot, it ensures that a read will
occur before the fastest 1-Wire device(s) releases the line.
15)
The duration of the low pulse sent by the master should be a minimum of 1
μ
s with a maximum value
as short as possible to allow time for the pullup resistor to recover the line to a high level before the 1-
Wire device samples in the case of a Write-One Time or before the master samples in the case of a
Read-One Time.
16)
Guaranteed by design; not production tested.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS243 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| DS2430 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:256-Bit 1-Wire EEPROM |
| DS2430A | 功能描述:電可擦除可編程只讀存儲器 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| DS2430A R | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:256-Bit 1-Wire EEPROM |
| DS2430A T | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:256-Bit 1-Wire EEPROM |
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