- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376968 > DS2430AP The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each PDF資料下載
參數(shù)資料
| 型號： | DS2430AP |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 357K |
| 代理商： | DS2430AP |
DS2430A
12 of 16
102199
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual
example.
1-Wire Signaling
The DS2430A requires strict protocols to insure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read
Data. All these signals except presence pulse are initiated by the bus master. The initialization sequence
required to begin any communication with the DS2430A is shown in Figure 9. A reset pulse followed by
a presence pulse indicates the DS2430A is ready to accept a ROM command. The bus master transmits
(TX) a reset pulse (t
RSTL
, minimum 480 μs). The bus master then releases the line and goes into receive
mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After detecting the rising edge
on the data pin, the DS2430A waits (t
PDH
, 15-60 μs) and then transmits the presence pulse (t
PDL
, 60-240
μs).
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES”
Figure 9
In order not to mask interrupt signaling by other devices on the 1-Wire bus, t
RSTL
+ t
R
should always be
less than 960 μs.
Read/Write Time Slots
The definitions of write and read time slots are illustrated in Figure 10. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2430A to the
master by triggering a delay circuit in the DS2430A. During write time slots, the delay circuit determines
when the DS2430A will sample the data line. For a read data time slot, if a “0” is to be transmitted, the
delay circuit determines how long the DS2430A will hold the data line low overriding the 1 generated by
the master. If the data bit is a “1”, the DS2430A will leave the read data time slot unchanged.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2430AT | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| DS2430AV | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| DS2430AX | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| DS2430E | NVRAM (EEPROM Based) |
| DS2430EN | NVRAM (EEPROM Based) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2430AP R | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:256-Bit 1-Wire EEPROM |
| DS2430AP T | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:256-Bit 1-Wire EEPROM |
| DS2430AP/R | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:256-Bit 1-Wire EEPROM |
| DS2430AP/T | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:256-Bit 1-Wire EEPROM |
| DS2430AP/T&R | 功能描述:電可擦除可編程只讀存儲器 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。