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參數(shù)資料
| 型號(hào)： | DS2430AP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 357K |
| 代理商： | DS2430AP |
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DS2430A
9 of 16
102199
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances, the
DS2430A is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal type and timing). A 1-Wire protocol defines bus transactions in terms of the bus state
during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain connection or 3-state outputs. The 1-Wire port of the DS2430A is open drain with an internal circuit
equivalent to that shown in Figure 7. A multidrop bus consists of a 1-Wire bus with multiple slaves
attached. The 1-Wire bus has a maximum data rate of 16.3k bits per second and requires a pullup resistor
of approximately 5 k
.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 120 μs, one or more of the devices on the bus may be reset.
HARDWARE CONFIGURATION
Figure 7
*5 k
is adequate for reading the DS2430A. To write to a single device, a 2.2 k
resistor and V
PUP
of at
least 4.0V is sufficient. For writing multiple DS2430As simultaneously or operation at low V
PUP
, the
resistor should be bypassed by a low-impedance pullup to V
PUP
while the device copies the scratchpad to
EEPROM.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2430AT | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| DS2430AV | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| DS2430AX | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| DS2430E | NVRAM (EEPROM Based) |
| DS2430EN | NVRAM (EEPROM Based) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2430AP R | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:256-Bit 1-Wire EEPROM |
| DS2430AP T | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:256-Bit 1-Wire EEPROM |
| DS2430AP/R | 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:256-Bit 1-Wire EEPROM |
| DS2430AP/T | 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:256-Bit 1-Wire EEPROM |
| DS2430AP/T&R | 功能描述:電可擦除可編程只讀存儲(chǔ)器 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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