參數(shù)資料
型號: DS26334GNA3+
廠商: Maxim Integrated Products
文件頁數(shù): 25/121頁
文件大?。?/td> 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 16/16
規(guī)程: IEEE 1149.1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA,CSBGA
供應(yīng)商設(shè)備封裝: 256-CSBGA(17x17)
包裝: 托盤
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
120 of 121
13 DATA SHEET REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
070105
Initial release.
012507
Added descriptions of feature enhancements implemented in revision A2:
1) Programmable corner frequency for the jitter attenuator in E1 mode.
2) Fully internal impedance matching option for RTIP/RRING.
3) Option for system-side deployment of BERT.
4) Revised B8ZS/HDB3 sections for clarification of functions.
5) Added RESREF pin for receive termination calibration.
See below for the detailed list of changes made to this data sheet revision.
See Features bullets, Detailed Description, and Section 5.5.1 for mention of fully
internal receive impedance matching.
1, 7, 27
Added RESREF pin (R9).
11
In OE pin description, changed GC.RTCTL to TST.RHPMC
15
Deleted R9 from DVSS.
16
In Section 5.4: Transmitter, second paragraph, changed NRZ encoding to AMI
encoding.
20
Replaced Figure 5-8.
25
In Table 5-6, updated Rt; updated Section 5.4.3 and Section 5.4.4; in Section 5.4.5:
Zero Suppression—B8ZS or HDB3, removed last sentence from first paragraph.
26
Changed Section 5.4.8 name from Drive Failure Monitor to Driver Fail Monitor;
updated Section 5.5; added new Section 5.5.1: Receive Impedance Matching
Calibration.
27
Added Section 5.5.8: Receive Dual-Rail Mode; added new Section 5.5.9: Receive
Single-Rail Mode; updated Table 5-11.
30
Updated Section 5.8.2: Digital Loopback.
33
Added new paragraph to Section 5.9: BERT.
34
Changed GMC to BGMC (Table 6-1) (see also page 53).
40
In Table 6-4, deleted Receive Bit Error Count Register 4 (does not exist for this
part).
43
In Table 6-5, changed bit names for LOSS (LIUs 1–16) to correctly match bit
description on page 49; for TST, changed bits 7–5 from Reserved to JABWS1,
JABWS0, and RHPMC (see also page 58).
44
In Table 6-6, changed SRS bit to correctly say SRMS.
45
In Table 6-7, added missing address (27) to SHLHS for LIUs 9–16; changed bit 7
and bits 3–0 names for RSMM4 (LIUs 9–16) to correctly match bit description on
page 74; changed “GISC” (3E) to “Not Used” for LIUs 9–16.
46
In Table 6-8, changed BSR register bit 3 (PMS) to show it is read only (added
underline), matching the bit description on page 88, as well as changed “RW” to “R”
to correctly show all bits are read only; changed BSRL register bit 3 (PMSL) to show
it is read only (added underline), matching the bit description on page 89, as well as
changed “RL/W” to “R” to correctly show all bits are read only.
47
In the LOSS register, corrected bit names from LOS[8:1] to LOSS[8:1].
49
Changed GMC to BGMC; changed bits 7, 6, and 5 from Reserved to BERTDIR,
BMCKS, and BTCKS.
53
In the GC register (LIUs 1–8), changed bit 7 from Reserved to RIMPMS and bit 2
from RTCTL to CRIMP (see also page 44, Table 6-5).
56
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