參數(shù)資料
型號: DS26334GNA3+
廠商: Maxim Integrated Products
文件頁數(shù): 76/121頁
文件大?。?/td> 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 16/16
規(guī)程: IEEE 1149.1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA,CSBGA
供應(yīng)商設(shè)備封裝: 256-CSBGA(17x17)
包裝: 托盤
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
58 of 121
Register Name:
TST
Register Description:
Template Select Transmitter Register
Register Address (LIUs 1–8):
10h
Bit #
7
6
5
4
3
2
1
0
Name
JABWS1
JABWS0
RHPMC
TST2
TST1
TST0
Default
0
Bits 7 and 6: Jitter Attenuator Bandwidth Selection [1:0] (JABWS[1:0]). In E1 mode, JABWS[1:0] is used to
control the bandwidth of the jitter attenuator according to the following table:
JABWS
BANDWIDTH (Hz)
00
0.625
01
1.25
10
2.5
11
5
Bit 5: Receive Hitless Protection Mode Control (RHPMC). When this bit is set, the receive impedance match
on/off selection will be controlled by the OE pin. If OE is high, receive impedance match is on. If OE is low, receive
impedance match is off (Internal impedance to RTIP and RRING is high impedance). When this bit is reset, the
RIMPON register bit will control receive impedance match.
Bits 2 to 0: TST Template Select Transceiver [2:0] (TST[2:0]). TST[2:0] is used to select the transceiver that the
Transmit Template Select Register (0x11) will configure for LIUs 1–8. See Table 6-11.
Register Address (LIUs 9–16):
30h
Bit #
7
6
5
4
3
2
1
0
Name
JABWS1
JABWS0
RHPMC
TST2
TST1
TST0
Default
0
Bits 7 and 6: Jitter Attenuator Bandwidth Selection [1:0] (JABWS[1:0]). In E1 mode, JABWS[1:0] is used to
control the bandwidth of the jitter attenuator according to the following table:
JABWS
BANDWIDTH (Hz)
00
0.625
01
1.25
10
2.5
11
5
Bit 5: Receive Hitless Protection Mode Control (RHPMC). When this bit is set, the receive impedance match
on/off selection will be controlled by the OE pin. If OE is high, receive impedance match is on. If OE is low, receive
impedance match is off (internal impedance to RTIP and RRING is high impedance). When this bit is reset, the
RIMPON register bit will control receive impedance match.
Bits 2 to 0: TST Template Select Transceiver [2:0] (TST[2:0]). TST[2:0] is used to select the transceiver that the
Transmit Template Select Register (0x11) will configure for LIUs 9–16. See Table 6-12.
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