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參數(shù)資料
| 型號(hào)： | DS26504LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 11/129頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC T1/E1/J1 64KCC ELEMENT 64LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 功能： | BITS 元件 |
| 接口： | 64KCC，E1，T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 電流 - 電源： | 150mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
| 包括： | * |
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DS26504 T1/E1/J1/64KCC BITS Element
108 of 129
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code will be loaded into the identification register on the
rising edge of JTCLK following entry into the capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a 1 in the LSB position. The next
11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits
for the device and 4 bits for the version Table 17-2. Table 17-3 lists the device ID codes.
Table 17-2. ID Code Structure
MSB
LSB
Version
Contact Factory
Device ID
JEDEC
1
4 bits
16 bits
00010100001
1
Table 17-3. Device ID Codes
DEVICE
16-BIT ID
DS26502
0035h
DS26503
0036h
DS26504
0034h
17.2 Test Registers
IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register.
An optional test register has been included with the DS26504 design. This test register is the
identification register and is used with the IDCODE instruction and the Test-Logic-Reset state of the TAP
controller.
17.3 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is n bits in length. See Table 17-4 for the cell bit locations and definitions.
17.4 Bypass Register
This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that
provides a short path between JTDI and JTDO.
17.5 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26504LN+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS26504LN+T&R | 制造商:Maxim Integrated Products 功能描述:T1/E1/J1 ENH BITS IC LQFP LF T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC T1/E1/J1 64KCC ELEMENT 64LQFP |
| DS26504LN+T&R | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26504LNB2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26504LNB2+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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