DS26518 8-Port T1/E1/J1 Transceiver
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9.8
System Backplane Interface
The DS26518 provides a versatile backplane interface that can be configured to:
Transmit and receive two-frame elastic stores
Mapping of T1 channels into a 2.048MHz backplane
IBO mode for multiple framers to share the backplane signals
Transmit and receive channel blocking capability
Fractional T1/E1/J1 support
Hardware-based (through the backplane interface) or processor-based signaling
Flexible backplane clock providing frequencies of 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz
Backplane clock and frame pulse (TSSYNCIOn) generator
9.8.1 Elastic Stores
The DS26518 contains dual, two-frame elastic stores for each framer: one for the receive direction and one for the
transmit direction. Both elastic stores are fully independent. The transmit- and receive-side elastic stores can be
enabled/disabled independently of each other. Also, the transmit or receive elastic store can interface to either a
1.544MHz or 2.048/4.096/8.192/16.384MHz backplane without regard to the backplane rate for the other elastic
store. All eight channels have their own TSYSCLKn/RSYSCLKn pins, allowing a unique backplane system clock for
each channel. This allows for maximum flexibility in the design of the backplane clock structure.
The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26518 is in
the T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane. In E1 mode the
elastic store can rate convert the E1 data stream to a 1.544MHz backplane. Second, they can be used to absorb
the differences in phase and frequency between the T1 or E1 clock and an asynchronous (i.e., not locked)
backplane clock, which can be 1.544MHz or 2.048MHz. If the two clocks are not frequency locked, the elastic
stores manage the rate difference and perform controlled slips, deleting or repeating frames of data in order to
manage the difference between the network and the backplane.
If the elastic store is enabled while in E1 mode, then either CAS or CRC4 multiframe boundaries are indicated via
the RMSYNCn output as controlled by the RSMS2 control bit (
RIOCR.1). If the user selects to apply a 1.544MHz
clock to the RSYSCLKn pin, the Receive Blank Channel Select Registers
(RBCS1–4) determine which channels of
the received E1 data stream will be deleted. In this mode an F-bit location is inserted into the RSERn data and set
to one. Also, in 1.544MHz applications, the RCHBLKn output will not be active in channels 25 to 32 (or in other
words, RCBR4 is not active). If the two-frame elastic buffer either fills or empties, a controlled slip will occur. If the
buffer empties, then a full frame of data will be repeated at RSERn and the
RLS4.5 and
RLS4.6 bits will be set to a
one. If the buffer fills, then a full frame of data will be deleted and the
RLS4.5 and
RLS4.7 bits will be set to a one.
The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the
Interleave Bus Option (IBO), which is discussed in Section
9.8.2.
Table 9-3 shows the registers related to the
elastic stores.
Table 9-3. Registers Related to the Elastic Store
REGISTER
FRAMER 1
ADDRESSES
FUNCTION
Receive I/O Configuration Register (
RIOCR)
084h
Sync and clock selection for the receiver.
Receive Elastic Store Control Register
085h
Receive elastic store control.
Receive Latched Status Register 4 (
RLS4)
093h
Receive elastic store empty full status.
Receive Interrupt Mask Register 4(
RIM4)
0A3h
Receive interrupt mask for elastic store.
Transmit Elastic Store Control Register
185h
Transmit elastic control such as minimum mode.
Transmit Latched Status Register 1
(TLS1)190h
Transmit elastic store latched status.
Transmit Interrupt Mask Register 1 (
TIM1)
1A0h
Transmit elastic store interrupt mask.
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8.