參數(shù)資料
型號： DS2890X-000
廠商： Maxim Integrated Products
文件頁數(shù)： 9/27頁
文件大?。?/td> 0K
描述： IC POT DIGITAL 1-WIRE 100K CSP
標準包裝： 10,000
接片： 256
電阻（歐姆）： 100k
電路數(shù)： 1
溫度系數(shù)： 標準值 800 ppm/°C
存儲器類型： 易失
接口： 1 線 串行
電源電壓： 2.8 V ~ 6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 6-XBGA，F(xiàn)CBGA
供應商設備封裝： 6-覆晶（2.82x2.54）
包裝： 帶卷 (TR)
DS2890
17 of 27
MASTER MODE
DATA (LSB FIRST)
COMMENTS
TX
C3h
Issue Wiper Increment Command
RX
<data byte>
Read new wiper position
TX
C3h
Issue Wiper Increment Command
RX
<data byte>
Read new wiper position
TX
99h
Issue Wiper Decrement Command
RX
<data byte>
Read new wiper position
TX
Reset
Reset Pulse
1-WIRE SIGNALING
The DS2890 requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read
Data. Except for the presence pulse the bus master initiates all these signals. The DS2890 can
communicate at two different speeds, regular speed and Overdrive Speed. If not explicitly set into the
Overdrive mode, the DS2890 will communicate at regular speed. While in Overdrive Mode the fast
timing applies to all waveforms.
The initialization sequence required to begin any communication with the DS2890 is shown in
Figure 16. A Reset Pulse followed by a Presence Pulse indicates the DS2890 is ready to send or receive
data. The bus master transmits (TX) a reset pulse (tRSTL, minimum 480 s at regular speed, 48 s at
Overdrive Speed). The bus master then releases the line and goes into receive mode (RX). The 1-Wire
bus is pulled to a high state via the pull-up resistor. After detecting the rising edge on the data contact, the
DS2890 waits (tPDH, 15-60 s at regular speed, 2-6 s at Overdrive speed) and then transmits the
Presence Pulse (tPDL, 60-240 s at regular speed, 8-24 s at Overdrive Speed). A Reset Pulse of 480 s or
longer will exit the Overdrive Mode returning the device to regular speed. If the DS2890 is in Overdrive
Mode and the Reset Pulse is no longer than 80 s the device will remain in Overdrive Mode.
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 17 (a-c). The master initiates all time
slots by driving the data line low. The falling edge of the data line synchronizes the DS2890 to the master
by triggering an internal timing circuit. During write time slots, the timing circuit determines when the
DS2890 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the timing circuit
determines how long the DS2890 will hold the data line low. If the data bit is a “1”, the DS2890 will not
hold the data line low at all.
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