參數(shù)資料
型號(hào)： DS3152+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 16/61頁(yè)
文件大?。?/td> 0K
描述： IC LIU DS3/E3/STS-1 144-CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： DS3
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 144-BGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-TECSBGA（13x13）
包裝： 托盤
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
23 of 61
For E3 RLOS Assertion:
1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is less than or equal to a signal
level approximately 24dB below nominal, and mutes the data coming out of the clock and data recovery block.
(24dB below nominal in the “tolerance range” of G.775, where LOS may or may not be declared.)
2) The DLOS detector counts 175
±75 consecutive zeros coming out of the CDR block and asserts RLOS. (175
±75 meets the 10 ≤ N ≤ 255 pulse-interval duration requirement of G.775.)
For E3 RLOS Clear:
1) The ALOS detector in the AGC/equalizer block detects that the incoming signal is greater than or equal to a
signal level approximately 18dB below nominal, and enables data to come out of the CDR block. (18dB is in
the “tolerance range” of G.775, where LOS may or may not be declared.)
2) The DLOS detector counts 175
±75 consecutive pulse intervals without EXZ occurrences and deasserts
RLOS. (175
±75 meets the 10 ≤ N ≤ 255 pulse-interval duration requirement of G.775.)
The DLOS detector supports the requirements of ANSI T1.231 for STS-1 LOS defects. At STS-1 rates, the time
required for the DLOS detector to count 175
±75 consecutive zeros falls in the range of 2.3≤ T≤ 100μs required by
ANSI T1.231 for declaring an LOS defect. Although the time required for the DLOS detector to count 175
±75
consecutive pulse intervals with no excessive zeros is less than the 125
μs–250μs period required by ANSI T1.231
for clearing an LOS defect, a period of this length where LOS is inactive can easily be timed in software.
During LOS, the RCLK output pin is derived from the LIU’s master clock. The ALOS detector has a longer time
constant than the DLOS detector. Thus, when the incoming signal is lost, the DLOS detector activates first
(asserting the RLOS pin or bit), followed by the ALOS detector. When a signal is restored, the DLOS detector does
not get a valid signal that it can qualify for no EXZ occurrences until the ALOS detector has seen the signal rise
above a signal level approximately 18dB below nominal.
Framer Interface Format and the B3ZS/HDB3 Decoder. The recovered data can be output in either binary or
bipolar format. To select the bipolar interface format, pull the RBIN pin low (hardware mode) or clear the RBIN
configuration bit (CPU bus mode). In bipolar format, the B3ZS/HDB3 decoder is disabled and the recovered data is
buffered and output on the RPOS and RNEG outputs. Received positive-polarity pulses are indicated by RPOS =
1, while negative-polarity pulses are indicated by RNEG = 1. In bipolar interface format, the receiver simply passes
on the received data and does not check it for BPV or EXZ occurrences.
To select the binary interface format, pull the RBIN pin high (hardware mode) or set the RBIN configuration bit
(CPU bus mode). In binary format, the B3ZS/HBD3 decoder is enabled, and the recovered data is decoded and
output as a binary value on the RDAT pin. Code violations are flagged on the RLCV pin. In the discussion that
follows, a valid pulse that conforms to the AMI rule is denoted as B. A BPV pulse that violates the AMI rule is
denoted as V.
In DS3 and STS-1 modes, B3ZS decoding is performed. RLCV is asserted during any RCLK cycle where the data
on RDAT causes ones of the following code violations:
Hardware mode or ITU bit set to 0
–
A BPV immediately preceded by a valid pulse (B, V).
–
A BPV with the same polarity as the last BPV.
–
The third zero in an EXZ occurrence.
ITU bit set to 1
–
A BPV immediately preceded by a valid pulse (B, V).
–
A BPV with the same polarity as the last BPV.
In E3 mode, HDB3 decoding is performed. RLCV is asserted during any RCLK cycle where the data on RDAT
causes one of the following code violations:
Hardware mode or ITU bit set to 0
–
A BPV immediately preceded by a valid pulse (B, V) or by a valid pulse and a zero (B, 0, V).
–
A BPV with the same polarity as the last BPV.
–
The fourth zero in an EXZ occurrence (only in hardware mode or when ITU = 0).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3152+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Dual DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3152B1 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Dual DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3152N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Dual DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3152N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Dual DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3153 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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