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參數(shù)資料
| 型號： | DS324 |
| 廠商： | Spansion Inc. |
| 英文描述： | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory |
| 中文描述： | 32兆位（4個M × 8位/ 2米x 16位），1.8伏的CMOS只，同時作業(yè)快閃記憶體 |
| 文件頁數(shù)： | 11/52頁 |
| 文件大?。?/td> | 604K |
| 代理商： | DS324 |
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10
Am29DS32xG
May 15, 2002
A D V A N C E I N F O R M A T I O N
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC5
in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
READY
(not during Embedded
Algorithms). The system can read data t
RH
after the
RESET# pin returns to V
IH
.
I
CC4
in the DC Characteristics table represents the
reset current. Also refer to AC Characteristics tables
for RESET# timing parameters and to Figure 14 for
the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 2.
Device Bank Divisions
Device
Part Number
Bank 1
Bank 2
Megabits
Sector Sizes
Megabits
Sector Sizes
Am29DS322G
4 Mbit
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
28 Mbit
Fifty-six
64 Kbyte/32 Kword
Am29DS323G
8 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
24 Mbit
Forty-eight
64 Kbyte/32 Kword
Am29DS324G
16 Mbit
Eight 8 Kbyte/4 Kword,
thrity-one 64 Kbyte/32 Kword
16 Mbit
Thirty-two
64 Kbyte/32 Kword
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