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參數(shù)資料
| 型號： | DS3253N# |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU DS3/E3/STS-1 144-CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 3/3 |
| 規(guī)程： | IEEE 1149.1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 144-TECSBGA（13x13） |
| 包裝： | 管件 |
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DS3251/DS3252/DS3253/DS3254
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Status Register Description
The status registers have two types of status bits. Real-time status bits—located in the SR registers—indicate the
state of a signal at the time it was read. Latched status bits—located in the SRL registers—are set when a signal
changes state (low-to-high, high-to-low, or both, depending on the bit) and cleared when written with a logic 1
value. After clearing, latched status bits remain cleared until the signal changes state again. Interrupt-enable bits—
located in the SRIE registers—control whether or not the
INT pin is driven low when latched register bits are set.
Figure 7-1. Status Register Logic
Register Name:
GCRn
Register Description:
Global Configuration Register
Register Address:
00h, 10h, 20h, 30h
Bit
7
6
5
4
3
2
1
0
Name
E3M
STS
LLB
RLB
TDSA
TDSB
—
RST
Default
0
—
0
Bit 7: E3 Mode Enable (E3M)
0 = DS3 operation
1 = E3 or STS-1 operation
Bit 6: STS-1 Mode Enable (STS)
When E3M = 1,
0 = E3 operation
1 = STS-1 operation
When E3M = 0, STS selects the DS3 AIS pattern (Table 6-G).
Bits 5, 4: Local Loopback, Remote Loopback Select (LLB, RLB)
00 = no loopback
01 = remote loopback
10 = analog local loopback
11 = digital local loopback
Bits 3, 2: Transmitter Data Select (TDSA, TDSB). See Table 6-G for details.
Bit 0: Reset (RST). When this bit is high, the digital logic of the LIU is held in reset and all registers for that LIU
(except the RST bit) are forced to their default values. RST is cleared to 0 at power-up and when the
RST pin is
activated.
0 = normal operation
1 = reset LIU
WR
EVENT
LATCHED STATUS REGISTER
SET ON EVENT DETECT
CLEAR ON WRITE LOGIC 1
INT ENABLE
REGISTER
SR
SRL
INT
OTHER INT
SOURCE
REAL-TIME STATUS
LATCHED STATUS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3253N# | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3253N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3253NA3 | 制造商:Maxim Integrated Products 功能描述:DS3253 REV A3 - Rail/Tube |
| DS3254 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3254+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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