參數(shù)資料
型號(hào)： DS3254N
英文描述： Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
中文描述： 單/雙/三/四DS3/E3/STS-1柳斯
文件頁(yè)數(shù)： 32/71頁(yè)
文件大小： 925K
代理商： DS3254N
DS3251/DS3252/DS3253/DS3254
32 of 71
10.
Each LIU contains an on-board jitter attenuator that can be placed in the receive path or the transmit path or can
be disabled. The TJA and RJA pins (hardware mode) or the
TCR
:TJA and
RCR
:RJA control bits (CPU bus mode)
specify how the jitter attenuator is used. Setting TJA = RJA = 0 disables the jitter attenuator. To use the jitter
attenuator in the receive path, set RJA = 1 (with TJA = 0). To use it in the transmit path, set TJA = 1.
Figure 10-1
shows the minimum jitter attenuation for the device when the jitter attenuator is enabled.
Figure 10-1
also shows
the receive jitter transfer when the jitter attenuator is disabled.
The jitter attenuator consists of a narrowband PLL to retime the selected clock, a FIFO to buffer the associated
data while the clock is being retimed, and logic to prevent FIFO over/underflow in the presence of very large jitter
amplitudes. In hardware mode, only 16-bit and 32-bit FIFO depths are available. See
Table 6-I
. In CPU bus mode,
control bits
TCR
:JAL[1:0] set the FIFO depth to 16, 32, 64, or 128 bits.
The jitter attenuator requires a transmission-quality master clock (i.e., 20ppm frequency accuracy and low jitter).
When enabled in the receive path, the JA can obtain its master clock from the appropriate MCLK pin, from the
clock adapter block, or from the TCLK pin. When enabled in the transmit path, the JA can take its master clock
from the MCLK pin or from the clock adapter block, but not from the TCLK pin. The CDR block also uses the
selected master clock. See Section
12
for more information about master clocks and clock selection.
The JA has a loop bandwidth of master_clock 2,058,874 (see corner frequencies in
Figure 10-1
). The JA
attenuates jitter at frequencies higher than the loop bandwidth, while allowing jitter (and wander) at lower
frequencies to pass through relatively unaffected.
In CPU bus mode the jitter attenuator indicates the fill status of its FIFO buffer in the JAFL (JA full) and JAEL (JA
empty) status bits in the
SRL
register. The JA sets the JAFL bit to indicate that its buffer is full. When the buffer
becomes full, the JA momentarily increases the frequency of the read clock by 6250 ppm to avoid buffer overflow
and consequent data loss. In a similar manner, the JA sets the JAEL bit to indicate that its buffer is empty. When
the buffer becomes empty, the JA momentarily decreases the frequency of the read clock by 6250 ppm to avoid
buffer underflow and consequent data errors. During these momentary frequency adjustments, jitter is passed
through the JA to avoid over/underflow. If the phase noise or frequency offset of the write clock is large enough to
cause the buffer to overflow or underflow, the JA sets
both
the JAFL bit
and
the JAEL bit to indicate that data errors
have occurred.
JITTER ATTENUATOR
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DS3254N# 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254NA3 制造商:Maxim Integrated Products 功能描述:QUAD ENH DS3/E3 LIU REV A3 IND - Rail/Tube
DS3256 功能描述:網(wǎng)絡(luò)控制器與處理器 IC X6 T3/E3 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3256N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC X6 T3/E3 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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