參數(shù)資料
型號(hào): DS3254N
英文描述: Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
中文描述: 單/雙/三/四DS3/E3/STS-1柳斯
文件頁數(shù): 42/71頁
文件大?。?/td> 925K
代理商: DS3254N
DS3251/DS3252/DS3253/DS3254
42 of 71
Figure 16-2. JTAG TAP Controller State Machine
16.3 JTAG Instruction Register and Instructions
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the
TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in
the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage toward the serial output at JTDO. A
rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to the Update-
IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction
parallel output.
Table 16-A
shows the instructions supported by the DS325x and their respective operational binary
codes.
Table 16-A. JTAG Instruction Codes
INSTRUCTIONS
SELECTED REGISTER
INSTRUCTION CODES
SAMPLE/PRELOAD
Boundary Scan
BYPASS
Bypass
EXTEST
Boundary Scan
CLAMP
Bypass
HIGHZ
Bypass
IDCODE
Device Identification
010
111
000
011
100
001
Test-Logic-Reset
Run-Test/Idle
Select
DR-Scan
1
0
Capture-DR
1
0
Shift-DR
0
1
Exit1- DR
1
0
Pause-DR
1
Exit2-DR
1
Update-DR
0
0
1
Select
IR-Scan
1
0
Capture-IR
0
Shift-IR
0
1
Exit1-IR
1
0
Pause-IR
1
Exit2-IR
1
Update-IR
0
0
1
0
0
1
0
1
0
1
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