參數(shù)資料
型號: DS3901E+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 19/20頁
文件大?。?/td> 0K
描述: IC RESIST VAR TRPL 14TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接片: 256
電阻(歐姆): 20k,30k,50k
電路數(shù): 3
溫度系數(shù): 標(biāo)準(zhǔn)值 50 ppm/°C
存儲器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 2.4 V ~ 5.5 V
工作溫度: -40°C ~ 95°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 帶卷 (TR)
DS3901
Triple, 8-Bit NV Variable Resistor
with Dual Settings and User EEPROM
8
_____________________________________________________________________
Detailed Description
The DS3901 contains three configurable variable resis-
tors. The Block Diagram illustrates the features of the
DS3901. The following sections discuss these features
in detail.
Dual Bank Resistor Settings
The setting for each resistor can be loaded from one of
two possible registers. These registers are referred to
as “banks” with each resistor having a “Bank 0” and
“Bank 1” value. The bank to be loaded as the resistor
value is selected by the OR’ing of the BK_SEL pin logic
state and the BSC control bit (bit 3, register 84h). See
the Memory Map section for details. If the result of the
OR’ing is a 0, then all three resistors will use the values
stored in their Bank 0 locations. If the result is a 1, then
all three resistors will use the values stored in their
Bank 1 locations.
Shunt Resistor Switch
Resistor 0 has the option to have an external fixed resis-
tor connected to the L0 pin. This provides a means to
select between a standard full-scale resistor value and
an extended full-scale value. By default, the L0_SW bit
(bit 4 of the Configuration Register, 84h) is set to a value
of 0. When the L0_SW bit is 0, the internal connection
from the low side of Resistor 0 to ground is opened, and
the low terminal of Resistor 0 is only connected to the
L0 pin. This allows for an external resistor to be
attached to the L0 pin for an extended full-scale value.
By writing the switch control bit L0_SW to a 1, the low
terminal of Resistor 0 is internally connected to ground.
High-Impedance Function
There are two ways to place the resistors in a high-
impedance (Hi-Z) state. One way is to set the DIS pin to
a 1. This is done by either floating the pin (there is an
internal pullup resistor, RDIS) or by connecting DIS
directly to VCC. When the DIS pin is held high or left
floating, all three resistors are held in a high-impedance
state. The second method is to use bits 0 to 2 of the
Configuration Register (84h), to set each resistor to a
high-impedance state (see the Memory Map section for
details). The state of the DIS pin overrides the state of
the high-impedance control bits (see the Memory Map
section for details).
Slave Address Byte
The ADD_SEL pin is used to select the I2C address of
the DS3901. When the ADD_SEL pin is connected low,
the I2C address of the DS3901 is A2h. When the
ADD_SEL pin is connected high, the value stored in the
Slave Address register (9Fh) is used. The default value
for the Slave Address register is shown in the Memory
Map section. The Slave Address register can be pro-
grammed to one of 128 possible addresses since the
LSB of the Slave Address register is reserved as the
read/write bit for the I2C command structure.
Password Protection
The memory of the DS3901 is write-protected with a
two-level password scheme. All memory locations can
be read without a password, with the exception of the
Password Entry registers and Password Setting regis-
ters. Once the appropriate password is entered in the
Password Entry bytes (88 to 8Bh), the DS3901 will allow
write access to the memory areas designated for that
password. The setting for the PW1 password is written
in the PW1 Password Setting register (bytes 90 to 93h).
The setting for the PW2 password is written in the PW2
Password Setting register (bytes 94 to 97h). See the
Memory Map section for more details. Entering the PW2
password allows access to areas protected by the PW1
password.
When shipped from the factory, both password settings
are all zeroes. Likewise, every time the device is pow-
ered up the Password Entry register (SRAM) defaults to
all zeroes. If write protection is not desired, leave the
password setting at the factory default and ignore the
Password Entry register. Write protection goes into
effect once either or both default password settings
have been changed to unique values.
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