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參數(shù)資料
| 型號(hào)： | DS3902U-530+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIGITAL RESISTER EEPROM 8USOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 30k，50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±300 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.4 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 95°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 90-3902T+530 |
DS3902
Dual, NV, Variable Resistors
with User EEPROM
10
____________________________________________________________________
See Figure 2 for a read example using the repeated
START condition to specify the starting memory location.
Reading Multiple Bytes from a Slave: The read oper-
ation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the master
reads the last byte it NACKs to indicate the end of the
transfer and generates a stop condition. This can be
done with or without modifying the address counter’s
location before the read cycle.
Application Information
Using the Resistors as a Switch
By taking advantage of the resistor’s high-impedance
state, the resistors can be used as a digitally controlled
switch. Setting the resistor to position 0 is equivalent to
a logic low level. By using an external pull-up resistor, a
logic high level can be generated by setting the resistor
to the High-Z state.
Power Supply Decoupling
To achieve best results, it is highly recommended that a
decoupling capacitor is used on the IC power supply
pins. Typical values of decoupling capacitors are 0.01F
and 0.1F. Use a high-quality, ceramic, surface-mount
capacitor, and mount it as close as possible to the VCC
and GND pins of the IC to minimize lead inductance.
SLAVE
ADDRESS*
START
1
0
1
0
1
R/W
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
MSB
LSB
MSB
LSB
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
READ/
WRITE
REGISTER ADDRESS
b7
b6
b5
b4
b3
b2
b1
b0
DATA
STOP
SINGLE BYTE WRITE
-WRITE RESISTOR 0 TO MID
POSITION (7FH)
SINGLE BYTE WRITE
-SET RESISTOR 1 TO HI-Z
SINGLE BYTE READ
-READ RESISTOR 1
TWO BYTE WRITE
- ENTER THE PASSWORD.
START
STOP
1 0100010
00000 100
A2h
04h
START
REPEATED
START
A3h
MASTER
NACK
STOP
1 0100010
00000 011
03h
10100 011
1 0100010
00000 010
A2h
02h
STOP
RES VALUE
START 1 0100010
00000 001
A2h
01h
STOP
DATA
02h
7Fh
EXAMPLE 2-WIRE TRANSACTIONS (WHEN ADD_SEL TIED TO GND)
TYPICAL 2-WIRE WRITE TRANSACTION
* THE ADDRESS IS DETERMINED BY THE ADD_SEL PIN. THE EXAMPLES ASSUME ADD_SEL IS TIED TO
GND. IF THE ADD_SEL PIN WERE INSTEAD CONNECTED TO VCC. THEN THE ADDRESS WOULD BE DETERMINED
BY THE SLAVE ADDRESS REGISTER.
01 111 111
0 0 000 010
A2h
PW MSB
PW LSB
TWO BYTE READ
- READ BOTH RESISTORS IN ONE
TRANSACTION.
A)
C)
B)
D)
START
STOP
101000 10
000 00010
A2h
02h
A3h
1010 0011
RES 0
DATA
RES 1
DATA
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
MASTER
ACK
MASTER
NACK
REPEATED
START
Figure 2. I2C Communication Examples
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