參數(shù)資料
型號(hào): DS3903E-020/T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 6/11頁(yè)
文件大小: 0K
描述: IC POT NV TRIPLE 128POS 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接片: 128
電阻(歐姆): 10k,10k,90k
電路數(shù): 3
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類(lèi)型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
DS3903
Triple 128-Position Nonvolatile
Digital Potentiometer
4
______________________________________________________________________
Note 1:
All voltages are referenced to ground.
Note 2:
ISTBY specified for VCC equal to 3.0V and 5.0V while control port logic pins are driven to the appropriate
logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or VCC for the
corresponding inactive state. WP must be disconnected or connected high.
Note 3:
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
Note 4:
A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal.
If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released.
Note 5:
After this period, the first clock pulse is generated.
Note 6:
The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the
SCL signal.
Note 7:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIN MIN of
the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
Note 8:
CB—total capacitance of one bus line in picofarads, timing referenced to 0.9 x VCC and 0.1 x VCC.
Note 9:
EEPROM write begins after a stop condition occurs.
Note 10:
Absolute linearity is used to measure expected wiper voltage as determined by wiper position in a
voltage-divider configuration.
Note 11:
Relative linearity is used to determine the change of wiper voltage between two adjacent wiper positions
in a voltage-divider configuration.
Typical Operating Characteristics
(VCC = 5.0V, 10k
plots apply to both pot0 and pot2, TA = +25°C unless otherwise noted.)
10
20
30
40
50
60
70
80
90
100
0
W-L RESISTANCE
vs. WIPER SETTING (90k
)
DS3903
toc03
WIPER SETTING
W-L
RESISTANCE
(k
)
125
100
75
50
25
0
W-L RESISTANCE
vs. WIPER SETTING (10k
)
DS3903
toc02
WIPER SETTING
W-L
RESISTANCE
(k
)
125
100
75
50
25
0
2
4
6
8
10
0
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
DS3903
toc01
TEMPERATURE (
°C)
SUPPLY
CURRENT
(
A)
50
40
-30 -20 -10
10 20
030
20
40
60
80
100
120
140
160
0
-40
60 70 80
VCC = 5V
VCC = 3V
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