參數(shù)資料
型號(hào): DS3930E+T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 7/12頁(yè)
文件大?。?/td> 0K
描述: IC POT NV HEX I/O MEM 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接片: 256
電阻(歐姆): 16.5k
電路數(shù): 6
溫度系數(shù): 標(biāo)準(zhǔn)值 ±250 ppm/°C
存儲(chǔ)器類(lèi)型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
DS3930
Hex Nonvolatile Potentiometer with
I/O and Memory
4
______________________________________________________________________
Note 1:
All voltages are referenced to ground.
Note 2:
ISTBY specified for VCC equal 3.0V and 5.0V, SDA = SCL = VCC, and I/O0 = I/O1 = I/O2 = I/O3 = A0 = A1 = A2 = GND.
Note 3:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns
+250ns = 1250ns before the SCL line is released.
Note 4:
After this period, the first clock pulse is generated.
Note 5:
The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 6:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH MIN of the SCL sig-
nal) in order to bridge the undefined region of the falling edge of SCL.
Note 7:
CB—total capacitance of one bus line in picofarads, timing referenced to 0.9VCC and 0.1VCC.
Note 8:
EEPROM write begins after a STOP condition occurs.
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V; TA = -40°C to +85°C, unless otherwise specified.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fast mode
0
0.9
Data Hold Time (Notes 3, 5, 7)
tHD:DAT
Standard mode
0
0.9
s
Fast mode
100
Data Setup Time (Note 3)
tSU:DAT
Standard mode
250
ns
Fast mode
0.6
Start Setup Time (Note 3)
tSU:STA
Standard mode
4.7
s
Fast mode
20 + 0.1CB
300
Rise Time of Both SDA and SCL
Signals (Note 7)
tR
Standard mode
20 + 0.1CB
1000
ns
Fast mode
20 + 0.1CB
300
Fall Time of Both SDA and SCL
Signals (Note 7)
tF
Standard mode
20 + 0.1CB
300
ns
Fast mode
0.6
Setup Time for STOP Condition
tSU:STO
Standard mode
4.0
s
Capacitive Load for Each Bus
CB
(Note 7)
400
pF
EEPROM Write Time
tW
(Note 8)
5
20
ms
EEPROM CHARACTERISTICS
(VCC = +2.7V to +5.5V; TA = -40°C to +85°C, unless otherwise specified.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Writes
+70°C
50,000
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