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參數(shù)資料
| 型號： | DS4302Z-020+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 5-BIT SGL 0-2.0V 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 設(shè)置時間： | 10µs |
| 位數(shù)： | 5 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
DS4302
Detailed Description
The DS4302 contains a 5-bit DAC and three programma-
ble digital outputs. The DAC setting and the pro-
grammed output levels are contained in a 1-byte data
word that defaults to 00h on power-up (see Figure 1 for
data byte configuration). The upper 5 MSbits of the byte
set the DAC and control the voltage produced on VOUT.
A setting of 1111 1XXX sets the minimum output voltage
from the DAC while a setting of 0000 0XXX sets the maxi-
mum output voltage from the DAC. The three LSbits of
the data byte control the three output pins, P0, P1, and
P2. Setting any of these control bits to a 0 pulls the corre-
sponding outputs low and setting the bits to a 1 pulls the
outputs high.
The DS4302 communicates through a 2-wire (SMBus-
compatible) digital interface and has a 2-wire address of
58h. Write and read operations are used to access the
DAC and output settings. Each operation begins with a
2-wire START condition, consists of three bytes, and
ends with a 2-wire STOP condition (see Figure 2). Using
the write operation, the 2-wire master can program the
5-bit DAC to adjust the voltage on VOUT and set the
level of the three output pins: P0, P1, and P2. The read
operation is used to recall the programmed settings.
2-Wire Definitions
The following terminology is commonly used to
describe 2-wire data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START, and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle, it initiates a
low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 3 for
applicable timing.
STOP Condition: A STOP condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a STOP condition. See Figure 3 for applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (see Figure 3). Data is
shifted into the device during the rising edge of the SCL.
2-Wire, 5-Bit DAC with Three Digital Outputs
6
_____________________________________________________________________
DATA BYTE
MSB
DAC VALUE
P0
P2
P1
Figure 1. Data Byte Configuration
Figure 2. 2-Wire Communication Examples
S
P
A
START
8-BITS ADDRESS OR DATA
STOP
ACK
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
WRITE A SINGLE BYTE
AAh
READ A SINGLE BYTE
00h
59h
58h
COMMUNICATIONS KEY
S
XXX
X
XXX
X
010
1
100
0
A
DATA BYTE
A
P
NOTES:
1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
2) THE FIRST BYTE SENT AFTER A START CONDITION IS
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
READ/WRITE BIT.
0000
1111
S
01011001
A
DATA BYTE
A
P
00
0
0000
A
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| DS4302Z-020/T&R | 制造商:Maxim Integrated Products 功能描述:IC DAC 5-BIT SGL 0-2.0V 8-SOIC |
| DS4302Z-020/T&R | 功能描述:IC DAC 5-BIT SGL 0-2.0V 8-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:3,000 系列:nanoDAC™ 設(shè)置時間:80µs 位數(shù):18 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 供應(yīng)商設(shè)備封裝:SOT-23-8 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極 采樣率（每秒）:- 產(chǎn)品目錄頁面:784 (CN2011-ZH PDF) 配用:EVAL-AD5680EBZ-ND - BOARD EVAL FOR AD5680 其它名稱:AD5680BRJZ-2REEL7TR |
| DS4302Z-020+ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 2-Wire 5-Bit w/3 Digital Outputs RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DS4302Z-020+T&R | 制造商:Maxim Integrated Products 功能描述:DAC 1CH 5-BIT 8SOIC N - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC DAC 5-BIT SGL 0-2.0V 8-SOIC |
| DS4302Z-020+T&R | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 2-Wire 5-Bit w/3 Digital Outputs RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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