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| 型號： | DS5001FP-16 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 23/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 128K 16MHZ 80-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | DS500x |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，SIO，UART/USART |
| 外圍設(shè)備： | 電源故障復(fù)位，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | SRAM |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 80-BQFP |
| 包裝： | 托盤 |
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DS5001FP
5 of 27
PIN DESCRIPTION (continued)
PIN
80 PIN
44 PIN
NAME
FUNCTION
53, 16,
8, 18,
80, 76,
4, 6, 20,
24, 26,
28, 30,
33, 35,
37
41, 36,
42, 32,
30, 34,
35, 43,
1, 2, 3,
4, 5, 7,
9
BA14–
BA0
Byte-Wide Address Bus Bits 14–0. This bus is combined with the nonmultiplexed
data bus (BD7–0) to access NV SRAM. Decoding is performed using CE1 through
CE4
. Therefore, BA15 is not actually needed. Read/write access is controlled by
R/ W . BA14–0 connect directly to an 8k, 32k, or 128k SRAM. If an 8k RAM is
used, BA13 and BA14 are unconnected. If a 128k SRAM is used, the micro converts
CE2
and CE3 to serve as A16 and A15 respectively.
71, 69,
67, 65,
61, 59,
57, 55
28, 26,
24, 23,
21, 20,
19, 18
BD7–0
Byte-Wide Data Bus Bits 7–0. This 8-bit, bidirectional bus is combined with the
nonmultiplexed address bus (BA14–0) to access NV SRAM. Decoding is performed
on CE1 and CE2 . Read/write access is controlled by R/ W . BD7–0 connect directly to
an SRAM, and optionally to a real-time clock or other peripheral.
10
37
R/ W
Read/Write. This signal provides the write enable to the SRAMs on the byte-wide
bus. It is controlled by the memory map and partition. The blocks selected as
program (ROM) are write-protected.
74
29
CE1
Chip Enable 1. This is the primary decoded chip enable for memory access on the
byte-wide bus. It connects to the chip enable input of one SRAM. CE1 is lithium-
backed. It remains in a logic high inactive state when VCC falls below VLI.
72
—
CE1N
Non-Battery-Backed Version of Chip Enable 1. This can be used with a 32kB
EPROM. It should not be used with a battery-backed chip.
2
33
CE2
Chip Enable 2. This chip enable is provided to access a second 32k block of
memory. It connects to the chip enable input of one SRAM. When MSEL = 0, the
micro converts CE2 into A16 for a 128k x 8 SRAM. CE2 is lithium-backed and
remains at a logic high when VCC falls below VLI.
63
22
CE3
Chip Enable 3. This chip enable is provided to access a third 32k block of memory.
It connects to the chip enable input of one SRAM. When MSEL = 0, the micro
converts CE3 into A15 for a 128k x 8 SRAM. CE3 is lithium-backed and remains at
a logic high when VCC falls below VLI.
62
—
CE4
Chip Enable 4. This chip enable is provided to access a fourth 32k block of
memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, this
signal is unused. CE4 is lithium-backed and remains at a logic high when VCC < VLI.
78
—
PE1
Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh
when the PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-
time clock such as the DS1283. PE1 is lithium-backed and remains at a logic high
when VCC falls below VLI. Connect PE1 to battery-backed functions only.
3
—
PE2
Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh
when the PES bit is set to a logic 1. PE2 is lithium-backed and remains at a logic
high when VCC falls below VLI. Connect PE2 to battery-backed functions only.
22
—
PE3
Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh
when the PES bit is set to a logic 1. PE3 is not lithium-backed and can be connected
to any type of peripheral function. If connected to a battery-backed chip, it needs
additional circuitry to maintain the chip enable in an inactive state when VCC < VLI.
23
—
PE4
Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh
when the PES bit is set to a logic 1. PE4 is not lithium-backed and can be connected
to any type of peripheral function. If connected to a battery-backed chip, it needs
additional circuitry to maintain the chip enable in an inactive state when VCC < VLI.
32
—
PROG
Invokes the bootstrap loader on a falling edge. This signal should be debounced
so that only one edge is detected. If connected to ground, the micro enters bootstrap
loading on power-up. This signal is pulled up internally.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS5001FP-16+ | 功能描述:微處理器 - MPU Soft MCU Chip RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| DS5001FP-16N | 功能描述:微處理器 - MPU Soft MCU Chip RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| DS5001FP-16N+ | 功能描述:微處理器 - MPU Soft MCU Chip RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| DS5001FPN08 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| DS5001FPN12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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