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R01UH0025EJ0300 Rev. 3.00
Page xxi of xxxii
Sep 24, 2010
16.3.7
Serial Status Register (SCFSR)......................................................................... 688
16.3.8
Bit Rate Register (SCBRR)............................................................................... 696
16.3.9
FIFO Control Register (SCFCR) ...................................................................... 704
16.3.10
FIFO Data Count Register (SCFDR) ................................................................ 706
16.3.11
Serial Port Register (SCSPTR) ......................................................................... 707
16.3.12
Line Status Register (SCLSR) .......................................................................... 709
16.4
Operation .......................................................................................................................... 710
16.4.1
Overview........................................................................................................... 710
16.4.2
Operation in Asynchronous Mode .................................................................... 712
16.4.3
Operation in Clocked Synchronous Mode ........................................................ 721
16.5
SCIF Interrupts ................................................................................................................. 729
16.6
Usage Notes ...................................................................................................................... 730
16.6.1
SCFTDR Writing and TDFE Flag .................................................................... 730
16.6.2
SCFRDR Reading and RDF Flag ..................................................................... 730
16.6.3
Restriction on DMAC Usage ............................................................................ 731
16.6.4
Break Detection and Processing ....................................................................... 731
16.6.5
Sending a Break Signal..................................................................................... 731
16.6.6
Receive Data Sampling Timing and Receive Margin
(Asynchronous Mode) ...................................................................................... 732
Section 17 I
2C Bus Interface 3 (IIC3) ................................................................733
17.1
Features............................................................................................................................. 733
17.2
Input/Output Pins .............................................................................................................. 735
17.3
Register Descriptions ........................................................................................................ 736
17.3.1
I
2C Bus Control Register 1 (ICCR1) ................................................................. 737
17.3.2
I
2C Bus Control Register 2 (ICCR2) ................................................................. 740
17.3.3
I
2C Bus Mode Register (ICMR)........................................................................ 742
17.3.4
I
2C Bus Interrupt Enable Register (ICIER) ....................................................... 744
17.3.5
I
2C Bus Status Register (ICSR)......................................................................... 746
17.3.6
Slave Address Register (SAR) .......................................................................... 749
17.3.7
I
2C Bus Transmit Data Register (ICDRT)......................................................... 750
17.3.8
I
2C Bus Receive Data Register (ICDRR) .......................................................... 750
17.3.9
I
2C Bus Shift Register (ICDRS)........................................................................ 750
17.3.10
NF2CYC Register (NF2CYC) .......................................................................... 751
17.4
Operation .......................................................................................................................... 752
17.4.1
I
2C Bus Format.................................................................................................. 752
17.4.2
Master Transmit Operation ............................................................................... 753
17.4.3
Master Receive Operation................................................................................. 755
17.4.4
Slave Transmit Operation ................................................................................. 757
17.4.5
Slave Receive Operation................................................................................... 760