參數(shù)資料
型號(hào): DS80C310-QNG/T&R
廠商: Maxim Integrated Products
文件頁數(shù): 4/22頁
文件大小: 0K
描述: IC MCU HI SPEED 25MHZ IND 44PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: EBI/EMI,SIO,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR
輸入/輸出數(shù): 32
程序存儲(chǔ)器類型: ROMless
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 帶卷 (TR)
DS80C310
12 of 22
Note 6:
When addressing external memory. This specification applies to the first clock cycle following the transition. On subsequent
cycles following 1 to 0 transitions, the typical current sink capability of Port 0 and Port 2 is approximately 150
A, and the
minimum current sink capability of ALE and
PSEN is approximately 400
A. On subsequent cycles following 0 to 1
transitions, the typical current drive capability of Port 0 and Port 2 is approximately 110
A.
Note 7:
RST = VCC. This condition mimics operation of pins in I/O mode.
Note 8:
During a 0 to 1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in transition
mode.
Note 9:
Current required from external circuit to hold a logic-low level on an I/O pin while the corresponding port latch bit is set to 1.
This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin must also overcome the transition
current.
Note 10:
Ports 1 and 3 source transition current when being pulled down externally. The current reaches its maximum at approximately
2V.
Note 11:
0.45 < VIN <VCC. Not a high-impedance input. This port is a weak address holding latch because Port 0 is dedicated as an
address bus on the DS80C310. Peak current occurs near the input transition point of the latch, approximately 2V.
Figure 2. Typical ICC vs. Frequency
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