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參數(shù)資料
| 型號： | DS80C310-QNG/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU HI SPEED 25MHZ IND 44PLCC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 500 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 25MHz |
| 連通性： | EBI/EMI，SIO，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 帶卷 (TR) |
DS80C310
13 of 22
AC ELECTRICAL CHARACTERISTICS (Note 1)
25MHz
VARIABLE
CLOCK
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
External Oscillator
0
25
0
25
Oscillator
Frequency
External Crystal
1/tCLCL
1
25
1
25
MHz
ALE Pulse Width
tLHLL
40
1.5tCLCL-
5
ns
Port 0 Address Valid to ALE Low
tAVLL
10
0.5tCLCL-
5
ns
Address Hold after ALE Low
tLLAX1
2
(Note 2)
0.5tCLCL-
18
(Note 2)
ns
ALE Low to Valid Instruction In
tLLIV
56
2.5tCLCL-
20
ns
ALE Low to
PSEN Low
tLLPL
7
0.5tCLCL-
13
ns
PSEN Pulse Width
tPLPH
55
2tCLCL-5
ns
PSEN Low to Valid Instruction In
tPLIV
41
2tCLCL-
20
ns
Input Instruction Hold after
PSEN
tPXIX
0
ns
Input Instruction Float after
PSEN
tPXIZ
26
tCLCL-5
ns
Port 0 Address to Valid Instruction In
tAVIV1
71
3tCLCL-
20
ns
Port 2 Address to Valid Instruction In
tAVIV2
81
3.5tCLCL-
25
ns
PSEN Low to Address Float
tPLAZ
(Note 2)
ns
Note 1:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted. Specifications to -40
C
are guaranteed by design and not product tested. AC electrical characteristics assume 50% duty cycle for the oscillator, and
are not 100% tested but are guaranteed by design. All signals characterized with load capacitance of 80pF except Port 0, ALE,
PSEN, and WR with 100pF. Interfacing to memory devices with float times (turn-off times) over 25ns can cause contention.
This does not damage the parts, but rather causes an increase in operating current. Port 2 and ALE timing changes in relation
to duty cycle variation.
Note 2:
Address is held in a weak latch until overdriven by external memory.
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