參數(shù)資料
型號: DS80C320-ENG
廠商: Maxim Integrated Products
文件頁數(shù): 22/38頁
文件大?。?/td> 0K
描述: IC MCU HI SPEED 25MHZ IND 44TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 160
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: EBI/EMI,SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 32
程序存儲器類型: ROMless
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
29 of 38
EXTERNAL CLOCK CHARACTERISTICS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Clock High Time
tCHCX
10
ns
Clock Low Time
tCLCX
10
ns
Clock Rise Time
tCLCH
5
ns
Clock Fall Time
tCHCL
5
ns
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SM2 = 0;
12 clocks per cycle
12tCLCL
Serial Port Clock
Cycle Time
tXLXL
SM2 = 1;
4 clocks per cycle
4tCLCL
ns
SM2 = 0
12 clocks per cycle
10tCLCL
Output Data Setup to
Clock Rising Edge
tQVXH
SM2 = 1;
4 clocks per cycle
3tCLCL
ns
SM2 = 0
12 clocks per cycle
2tCLCL
Output Data Hold
from Clock Rising
tXHQX
SM2 = 1;
4 clocks per cycle
tCLCL
ns
SM2 = 0;
12 clocks per cycle
tCLCL
Input Data Hold After
Clock Rising
tXHDX
SM2 = 1;
4 clocks per cycle
tCLCL
ns
SM2 = 0;
12 clocks per cycle
11tCLCL
Clock Rising Edge to
Input Data Valid
tXHDV
SM2 = 1
4 clocks per cycle
2tCLCL
ns
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameter as such
devices, using the same symbols. For completeness, the following is an explanation of the symbols.
t
Time
A
Address
C
Clock
D
Input data
H
Logic level high
L
Logic level low
I
Instruction
P
PSEN
Q
Output data
R
RD
signal
V
Valid
W
WR
signal
X
No longer a valid logic level
Z
Tri-state
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