參數(shù)資料
型號(hào)： DS80C320-QNL/T&R
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 8/38頁(yè)
文件大?。?/td> 0K
描述： IC MCU HI SPEED 33MHZ IND 44PLCC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 500
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器類(lèi)型： ROMless
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 帶卷 (TR)
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
16 of 38
a 25MHz crystal frequency. Note that once the counter chain has reached a conclusion, the optional
interrupt is generated. Regardless of whether the user enables this interrupt, there are then 512 clocks left
until a reset occurs. There are 5 control bits in special function registers that affect the Watchdog Timer
and two status flags that report to the user. The Reset Watchdog Timer bit (WDCON.0) should be
asserted prior to modifying the Watchdog Timer Mode Select bits (WD1, WD0) to avoid corruption of
the watchdog count.
WDIF (WDCON.3) is the interrupt flag that is set when there are 512 clocks remaining until a reset
occurs. WTRF (WDCON.2) is the flag that is set when a Watchdog reset has occurred. This allows the
application software to determine the source of a reset.
Setting the EWT (WDCON.1) bit enables the Watchdog Timer. The bit is protected by timed access.
Setting the RWT (WDCON.0) bit restarts the Watchdog Timer for another full interval. Application
software must set this bit prior to the timeout. As mentioned previously, WD1 and 0 (CKCON .7 and 6)
select the timeout. Finally, the Watchdog Interrupt is enabled using EWDI (EIE.4).
INTERRUPTS
The DS80C320/DS80C323 provide 13 sources of interrupt with three priority levels. The Power-fail
Interrupt (PFI), if enabled, always has the highest priority. There are two remaining user-selectable
priorities: high and low. If two interrupts that have the same priority occur simultaneously, the natural
precedence given in Table 4 determines which is acted upon. Except for the PFI, all interrupts that are
new to the 8051 family have a lower natural priority than the originals.
Table 4. Interrupt Priority
NAME
FUNCTION
VECTOR
NATURAL
PRIORITY
OLD/NEW
PFI
Power-Fail Interrupt
33h j
1
New
INT0
External Interrupt 0
03h
2
Old
TF0
Timer 0
0Bh
3
Old
INT1
External Interrupt 1
13h
4
Old
TF1
Timer 1
1Bh
5
Old
SCON0
TI0 or RI0 from Serial Port 0
23h
6
Old
TF2
Timer 2
2Bh
7
Old
SCON1
TI1 or RI1 from Serial Port 1
3Bh
8
New
INT2
External Interrupt 2
43h
9
New
INT3
External Interrupt 3
4Bh
10
New
INT4
External Interrupt 4
53h
11
New
INT5
External Interrupt 5
5Bh
12
New
WDTI
Watchdog Timeout Interrupt
63h
13
New
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