參數(shù)資料
型號: DS80C320MCG
英文描述: (434.89 k)
中文描述: (434.89十一)
文件頁數(shù): 4/38頁
文件大?。?/td> 434K
代理商: DS80C320MCG
DS80C320/DS80C323
110196 4/38
PIN DESCRIPTION
Table 1
DIP
40
PLCC
44
TQFP
38
SIGNAL
NAME
V
CC
GND
DESCRIPTION
V
CC
+5V.
GND
Digital circuit ground.
RST – Input
. The RST input pin contains a schmitt voltage input to
recognize external active high Reset inputs. The pin also employs an
internal pull–down resistor to allow for a combination of wired OR
external Reset sources. An RC is not required for power–up, as the
device provides this function internally.
20
22, 23
16, 17
9
10
4
RST
18
19
20
21
14
15
XTAL2
XTAL1
XTAL1, XTAL2
The crystal oscillator pins XTAL1 and XTAL2 pro-
vide support for parallel resonant, AT cut crystals. XTAL1 acts also as
an input in the event that an external clock source is used in place of
a crystal. XTAL2 serves as the output of the crystal amplifier.
29
32
26
PSEN
PSEN – Output
. The Program Store Enable output. This signal is
commonly connected to external ROM memory as a chip enable.
PSEN will provide an active low pulse width of 2.25 XTAL1 cycles
with a period of four XTAL1 cycles. PSEN is driven high when data
memory (RAM) is being accessed through the bus and during a reset
condition.
30
33
27
ALE
ALE – Output
. The Address Latch Enable output functions as a clock
to latch the external address LSB from the multiplexed address/data
bus. This signal is commonly connected to the latch enable of an
external 373 family transparent latch. ALE has a pulse width of 1.5
XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high
when the device is in a Reset condition.
39
38
37
36
35
34
33
32
43
42
41
40
39
38
37
36
37
36
35
34
33
32
31
30
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0–7 (Port 0) – I/O.
Port 0 is the multiplexed address/data bus. Dur-
ing the time when ALE is high, the LSB of a memory address is pres-
ented. When ALE falls, the port transitions to a bidirectional data bus.
This bus is used to read external ROM and read/write external RAM
memory or peripherals. The Port 0 has no true port latch and can not
be written directly by software. The reset condition of Port 0 is high.
No pull–up resistors are needed.
1–8
2–9
40–44
1–3
P1.0–P1.7
Port 1 – I/O
. Port 1 functions as both an 8–bit bidirectional I/O port and
an alternate functional interface for Timer 2 I/O, new External Inter-
rupts, and new Serial Port 1. The reset condition of Port 1 is with all
bits at a logic 1. In this state, a weak pull–up holds the port high. This
condition also serves as an input mode, since any external circuit that
writes to the port will overcome the weak pull–up. When software
writes a 0 to any port pin, the device will activate a strong pull–down
that remains on until either a 1 is written or a reset occurs. Writing a
1 after the port has been at 0 will cause a strong transition driver to
turn on, followed by a weaker sustaining pull–up. Once the momen-
tary strong driver turns off, the port once again becomes the output
high (and input) state. The alternate modes of Port 1 are outlined as
follows:
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
40
41
42
43
44
1
2
3
Port
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate Function
T2
External I/O for Timer/Counter 2
T2EX
Timer/Counter 2 Capture/Reload Trigger
RXD1
Serial Port 1 Input
TXD1
Serial Port 1 Output
INT2
External Interrupt 2 (Positive Edge Detect)
INT3
External Interrupt 3 (Negative Edge Detect)
INT4
External Interrupt 4 (Positive Edge Detect)
INT5
External Interrupt 5 (Negative Edge Detect)
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