參數(shù)資料
型號: DS80C390-FCR+
廠商: Maxim Integrated Products
文件頁數(shù): 23/53頁
文件大小: 0K
描述: IC MPU CAN DUAL HS 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,EBI/EMI,SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 32
程序存儲器類型: ROMless
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 3.85 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 64-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 703 (CN2011-ZH PDF)
DS80C390 Dual CAN High-Speed Microprocessor
3 of 53
AC ELECTRICAL CHARACTERISTICS—(MULTIPLEXED ADDRESS/DATA BUS)
(Note 10, Note 11)
40MHz
VARIABLE CLOCK
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
External oscillator
0
40
0
40
Oscillator Frequency
1 / tCLCL
External crystal
1
40
1
40
MHz
ALE Pulse Width
tLHLL
0.375 tMCS
- 5
ns
Port 0 Instruction Address or
CE0–4
Valid to ALE Low
tAVLL
0.125 tMCS - 5
ns
Address Hold After ALE Low
tLLAX1
0.125 tMCS - 5
ns
ALE Low to Valid Instruction In
tLLIV
0.625 tMCS - 20
ns
ALE Low to
PSEN Low
tLLPL
0.125 tMCS - 5
ns
PSEN Pulse Width
tPLPH
0.5 tMCS - 8
ns
PSEN Low to Valid Instruction In
tPLIV
0.5 tMCS - 20
ns
Input Instruction Hold After
PSEN
tPXIX
0
ns
Input Instruction Float After
PSEN
tPXIZ
0.25 tMCS - 5
ns
Port 0 Address to Valid Instruction In
tAVIV1
0.75 tMCS - 22
ns
Port 2, 4 Address to Valid Instruction
In
tAVIV2
0.875 tMCS - 30
ns
PSEN Low to Address Float
tPLAZ
0
ns
Note 11:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted. The value tMCS is a function
of the machine cycle clock in terms of the processor’s input clock frequency. These relationships are described in the Stretch Value
Timing
table. All signals characterized with load capacitance of 80pF except Port 0, ALE,
PSEN, RD, and WR with 100pF.
Interfacing to memory devices with float times (turn off times) over 25ns can cause bus contention. This does not damage the
parts, but causes an increase in operating current. Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing
changes in relation to duty cycle variation. Some AC timing characteristic drawings contain references to the CLK signal. This
waveform is provided to assist in determining the relative occurrence of events and cannot be used to determine the timing of
signals relative to the external clock. AC timing is characterized and guaranteed by design but is not production tested.
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