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參數(shù)資料
| 型號： | DS80C390-FCR+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 28/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU CAN DUAL HS 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | CAN，EBI/EMI，SIO，UART/USART |
| 外圍設(shè)備： | 電源故障復(fù)位，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.85 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 64-LQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 703 (CN2011-ZH PDF) |
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DS80C390 Dual CAN High-Speed Microprocessor
34 of 53
40-BIT ACCUMULATOR
The accelerator also incorporates an automatic accumulator function, permitting the implementation of multiply-
and-accumulate and divide-and-accumulate functions without any additional delay. Each time the accelerator is
used for a multiply or divide operation, the result is transparently added to a 40-bit accumulator. This can greatly
increase speed of DSP and other high-level math operations.
The accumulator can be accessed anytime the multiply/accumulate status flag (MCNT1;D2h) is cleared. The
accumulator is initialized by performing five writes to the multiplier C register (MC;D5h), LSB first. The 40-bit
accumulator can be read by performing five reads of the multiplier C register, MSB first.
MEMORY ADDRESSING
The DS80C390 incorporates three internal memory areas:
256 bytes of scratchpad (or direct) RAM
4kB of SRAM configurable as various combinations of MOVX data memory, stack memory, and MOVC
program memory
512 bytes of RAM reserved for the CAN message centers.
Up to 4MB of external memory is addressed via a multiplexed or demultiplexed 20-bit address bus/8-bit data bus
and four chip-enable (active during program memory access) or four peripheral-enable (active during data memory
access) signals. Three different addressing modes are supported, as selected by the AM1, AM0 bits in the ACON
SFR.
16-Bit Address Mode
Memory is accessed by 16-bit address mode similarly to the traditional 8051. It is op-code compatible with the 8051
microprocessor and identical to the byte and cycle count of the Dallas Semiconductor High-Speed Microcontroller
family. A device operating in this mode can access up to 64kB of program and data memory. The device defaults to
this mode following any reset.
22-Bit Paged-Address Mode
The 22-bit paged-address mode retains binary-code compatibility with the 8051 instruction set, but adds one
machine cycle to the ACALL, LCALL, RET, and RETI instructions with respect to Dallas Semiconductor’s High-
Speed Microcontroller family timing. This is transparent to standard 8051 compilers. Interrupt latency is also
increased by one machine cycle. In this mode, interrupt vectors are fetched from 0000xxh.
22-Bit Contiguous Address Mode
The 22-bit contiguous addressing mode uses a full 22-bit program counter, and all modified branching instructions
automatically save and restore the entire program counter. The 22-bit branching instructions such as ACALL,
AJMP, LCALL, LJMP, MOV DPTR, RET, and RETI instructions require an assembler, compiler, and linker that
specifically supports these features. The INC DPTR is lengthened by one cycle but remains byte-count-compatible
with the standard 8051 instruction set.
Internally, the device uses a 22-bit program counter. The lowest order 22 bits are used for memory addressing,
with a special 23rd bit used to map the 4kB SRAM above the 4MB memory space in bootstrap loader applications.
Address bits 16–23 for the 22-bit addressing modes are generated through additional SFRs dependent on the type
of instruction as shown in Table 4.
Table 4. Extended Address Generation
INSTRUCTION
ADDRESS BITS
23–16
ADDRESS BITS
15–8
ADDRESS BITS
7–0
MOVX instructions using DPTR
DPX;93h
DPH;83h
DPL;82h
MOVX instructions using DPTR1
DPX1;95h
DPH1;85h
DPL1;84h
MOVX instructions using @Ri
MXAX;EAh
P2;A0h
Ri
Addressing program memory in 22-bit
paged mode
AP;9Ch
—
10-bit stack pointer mode
—
ESP;9Bh
SP;81h
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS80C390-FCR+ | 功能描述:8位微控制器 -MCU Dual CAN High-Speed RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80C390-FNR | 功能描述:8位微控制器 -MCU Dual CAN High-Speed RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80C390-FNR+ | 功能描述:8位微控制器 -MCU Dual CAN High-Speed RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80C390-QCR | 功能描述:8位微控制器 -MCU Dual CAN High-Speed RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS80C390-QCR+ | 功能描述:8位微控制器 -MCU Dual CAN High-Speed RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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