參數(shù)資料
型號: DS80C390-QCR
元件分類: 微處理器
英文描述: Dual CAN High-Speed Microprocessor
中文描述: 雙CAN高速微處理器
文件頁數(shù): 24/58頁
文件大?。?/td> 5486K
代理商: DS80C390-QCR
DS80C390
24 of 58
110199
EXTERNAL RESET PINS
The DS80C390 has both reset input (RST) and reset output (
RSTOL
) pins. The
RSTOL
pin supplies an
active low Reset when the microprocessor is issued a Reset from either a high on the RST pin, a time out
of the watchdog timer, a crystal oscillator fail, or an internally detected power-fail. The timing of the
RSTOL
pin is dependent on the source of the reset.
Reset Type/Source
Power-on reset
External reset
Power fail
Watchdog timer reset
Oscillator fail detect
RSTOL
Duration
65536 t
CLCL
(as described in Power Cycle Timing Characteristics)
< 1.25 machine cycles
65536 t
CLCL
(as described in Power Cycle Timing Characteristics)
2 machine cycles
65536 t
CLCL
(as described in Power Cycle Timing Characteristics)
INTERRUPTS
The microcontroller provides 16 interrupt sources with three priority levels. All interrupts, with the
exception of the Power Fail interrupt, are controlled by a series combination of individual enable bits and
a global interrupt enable EA (IE.7). Setting EA to a 1 allows individual interrupts to be enabled.
Clearing EA disables all interrupts regardless of their individual enable settings.
The three available priority levels are low, high, and highest. The highest priority level is reserved for the
Power Fail Interrupt only. All other interrupt priority levels have individual priority bits that when set to
a 1 establish the particular interrupt as high priority. In addition to the user-selectable priorities, each
interrupt also has an inherent natural priority, used to determine the priority of simultaneously occurring
interrupts. The available interrupt sources, their flags, their enables, their natural priority, and their
available priority selection bits are identified in the following table.
INTERRUPT SUMMARY
Table 12
NAME
DESCRIPTION
VECTOR NATURAL
PRIORITY
33h
03h
0Bh
13h
1Bh
23h
FLAG BIT
ENABLE BIT
PRIORITY
CONTROL BIT
N/A
PX0(IP.0)
PT0(IP.1)
PX1(IP.2)
PT1(IP.3)
PS0(IP.4)
PFI
INT0
TF0
INT1
TF1
SCON0
Power Fail Interrupt
External Interrupt 0
Timer 0
External Interrupt 1
Timer 1
TI0 or RI0 from serial
port 0
Timer 2
TI1 or RI1 from serial
port 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
CAN0 Interrupt
CAN1 Interrupt
Watchdog Timer
CAN0/1 Bus Activity
0
1
2
3
4
5
PFI(WDCON.4)
IE0(TCON.1)**
TF0(TCON.5)*
IE1(TCON.3)**
TF1(TCON.7)*
RI_0(SCON0.0)
TI_0(SCON0.1)
TF2(T2CON.7)
RI_1(SCON1.0)
TI_1(SCON1.1)
IE2 (EXIF.4)
IE3 (EXIF.5)
IE4 (EXIF.6)
IE5 (EXIF.7)
various
various
WDIF (WDCON.3)
various
EPFI(WDCON.5)
EX0(IE.0)
ET0(IE.1)
EX1(IE.2)
ET1(IE.3)
ES0(IE.4)
TF2
SCON1
2Bh
3Bh
6
7
ET2(IE.5)
ES1(IE.6)
PT2(IP.7)
PS1(IP.6)
INT2
INT3
INT4
INT5
C0I
C1I
WDTI
CANBUS
Unless marked, all flags must be cleared by the application software.
*
Cleared automatically by hardware when the service routine is entered.
** If edge triggered, flag is cleared automatically by hardware when the service routine is entered. If
level triggered, flag follows the state of the interrupt pin.
43h
4Bh
53h
5Bh
6Bh
73h
63h
7Bh
8
9
10
11
12
13
14
15
EX2 (EIE.0)
EX3 (EIE.1)
EX4 (EIE.2)
EX5 (EIE.3)
C0IE (EIE.6)
C1IE (EIE.5)
EWDI (EIE.4)
CANBIE (EIE.7)
PX2 (EIP.0)
PX3 (EIP.1)
PX4 (EIP.2)
PX5 (EIP.3)
C0IP (EIP.6)
C1IP (EIP.5)
PWDI (EIP.4)
CANBIP (EIP.7)
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