DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
Table 3. Extended Address Generation
45 of 102
P4CNT.5–3
P6.5
P6.4
P4.7
P4.6
P4.5
P4.4
MAX MEMORY ACCESSIBLE
per
CE
32kB
(Note 1)
128kB
256kB
512kB
1MB
2MB (Note 4)
4MB
(Note 2)
000
001
010
011
100
101
I/O
I/O
I/O
I/O
I/O
I/O
A21
I/O
I/O
I/O
I/O
I/O
A20
A20
I/O
I/O
I/O
I/O
A19
A19
A19
I/O
I/O
I/O
A18
A18
A18
A18
I/O
I/O
A17
A17
A17
A17
A17
I/O
A16
A16
A16
A16
A16
A16
110 or 111(default)
Table 4. Chip-Enable Generation
PORT 6 PIN FUNCTION
P6.2
I/O
I/O
I/O
CE6
CE6
PORT 4 PIN FUNCTION
P4.2
I/O
I/O
I/O
CE2
CE2
P6CNT.2–0
P6.3
I/O
I/O
I/O
I/O
CE7
P6.1
I/O
I/O
CE5
CE5
CE5
P6.0
I/O
CE4
CE4
CE4
CE4
P4CNT.2–0
P4.3
I/O
I/O
I/O
I/O
CE3
P4.1
I/O
I/O
CE1
CE1
CE1
P4.0
I/O
CE0
CE0
CE0
CE0
000 (Note 3)
100
101
110
111 (Note 4)
000
100
101
110
111(default)
Note 1:
Only 32kB of memory is accessible per chip enable for the P4CNT.5-3 = 000b setting, which means at least two chip enables are
needed in order to address the standard 16-bit (0–FFFFh) address range.
Note 2:
The default P4CNT.5-3 = 111b setting (4MB accessible per
CE
) requires only four chip enables in order to access the maximum 24-bit
(0–FFFFFFh) address range.
Note 3:
Default condition when the internal ROM is disabled.
Note 4:
When the internal ROM is enabled, the default memory map is reconfigured to 2MB per
CE
, P4CNT.5-3 = 101b, and
CE4
to
CE7
are
enabled, P6CNT.2-0 = 111b.
External Data Memory Addressing
Using a similar implementation as was used to expand program memory access, the DS80C410 allows up to 4MB
of data memory access through four peripheral chip enables (
PCE
). The Port 5 control register (P5CNT; A2h) and
Port 6 control register (P6CNT; B2h) designate the number of peripheral chip enables and the maximum amount of
addressable data memory per peripheral chip enable.
Table 5
shows which port pins are converted to peripheral
chip enables, along with the maximum memory accessible through each peripheral chip enable for P5CNT, P6CNT
bit settings.
Table 5. Peripheral Chip-Enable Generation
P5CNT.2–0
000 (default)
100
101
110
111
P5.7
I/O
I/O
I/O
I/O
PCE3
P5.6
I/O
I/O
I/O
PCE2
PCE2
P5.5
I/O
I/O
PCE1
PCE1
PCE1
P5.4
I/O
PCE0
PCE0
PCE0
PCE0
P6CNT.5–3
000 (default)
001
010
011
100
MAX MEMORY ACSESSIBLE per
32kB
128kB
256kB
512kB
1MB
PCE
Demultiplexed External Memory Addressing
On power-up or following any reset, the DS80C410 defaults to the traditional 8051 external memory interface, with
the address MSB presented on Port 2 and the address LSB and data multiplexed on Port 0. The multiplexed mode
requires an external latch to demultiplex the address LSB and data. The DS80C410 provides an external pin (
MUX
)
that, when pulled high during a power-on reset, demultiplexes the address LSB and data. If demultiplexed mode is
enabled, the address LSB is provided on Port 7 and the data on Port 0. At the expense of consuming Port 7,
demultiplexed mode eliminates the external demultiplexing latch and the delay element associated with the latch. In
some cases, the removal of this timing delay allows use of slower, less expensive external memory devices.
Table 6
shows pin assignments for the multiplexed (traditional 8051) and demultiplexed external addressing
modes.