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參數(shù)資料
| 型號： | DS90LV031ATMTCX/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE DRIVER QUAD CMOS 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 驅(qū)動器 |
| 驅(qū)動器/接收器數(shù)： | 4/0 |
| 規(guī)程： | LVDS |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | DS90LV031ATMTCX |
SNLS020C – JULY 1999 – REVISED APRIL 2013
Switching Characteristics - Industrial
VCC = +3.3V ±10%, TA = 40°C to +85°C
(1) (2) (3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPHLD
Differential Propagation Delay High to Low
RL = 100, CL = 10 pF
0.8
1.18
2.0
ns
tPLHD
Differential Propagation Delay Low to High
0.8
1.25
2.0
ns
tSKD1
Differential Pulse Skew |tPHLD tPLHD|
(4)
0
0.07
0.4
ns
tSKD2
Channel-to-Channel Skew (5)
0
0.1
0.5
ns
tSKD3
Differential Part to Part Skew (6)
0
1.0
ns
tSKD4
Differential Part to Part Skew (7)
0
1.2
ns
tTLH
Rise Time
0.38
1.5
ns
tTHL
Fall Time
0.40
1.5
ns
tPHZ
Disable Time High to Z
RL = 100, CL = 10 pF
5
ns
tPLZ
Disable Time Low to Z
5
ns
tPZH
Enable Time Z to High
7
ns
tPZL
Enable Time Z to Low
7
ns
fMAX
Maximum Operating Frequency (8)
200
250
MHz
(1)
All typicals are given for: VCC = +3.3V, TA = +25°C.
(2)
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 1 ns, and tf ≤ 1 ns.
(3)
CL includes probe and jig capacitance.
(4)
tSKD1, |tPHLD tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(5)
tSKD2 is the Differential Channel-to-Channel Skew of any event on the same device.
(6)
tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation
delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(7)
tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max Min|
differential propagation delay.
(8)
fMAX generator input conditions: tr = tf < 1ns, (0% to 100%), 50% duty cycle, 0V to 3V. Output Criteria: duty cycle = 45%/55%, VOD >
250mV, all channels switching.
Copyright 1999–2013, Texas Instruments Incorporated
5
Product Folder Links: DS90LV031A
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