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參數(shù)資料
| 型號(hào)： | DSD1793DBR |
| 元件分類： | DAC |
| 英文描述： | 24 BIT 192 KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER |
| 中文描述： | 24位192千赫采樣高級(jí)分段音頻立體聲數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/47頁 |
| 文件大小： | 428K |
| 代理商： | DSD1793DBR |
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DSD1793
SLES075A MARCH 2003 REVISED JANUARY 2004
www.ti.com
20
FUNCTIONAL DESCRIPTIONS
Zero Detect
The DSD1793 has a zero-detect function. When the DSD1793 detects the zero conditions as shown in Table 2, the
DSD1793 sets ZEROL (pin 23) and ZEROR (pin 22) to HIGH.
Table 2. Zero Conditions
MODE
DETECTING CONDITION AND TIME
PCM
DATA is continuously LOW for 1024 LRCKs.
External DF mode
DATA is continuously LOW for 8
× 1024 WDCKs.
DSD
DZ0
There are an equal number of 1s and 0s in every 8 bits of DSD input data for 23 ms.
DSD
DZ1
The input data is 1001 0110 continuously for 23 ms.
Serial Control Interface (I2C)
The DSD1793 supports the I2C serial bus and the data transmission protocol for standard and fast mode as a slave
device. This protocol is explained in I2C specification 2.0.
Slave Address
MSB
LSB
1
0
1
ADR1
ADR0
R/W
The DSD1793 has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset
to 10011. The next two bits of the address byte are the device select bits, which can be user-defined by the ADR1
and ADR0 terminals. A maximum of four DSD1793s can be connected on the same bus at one time. Each DSD1793
responds when it receives its own slave address.
Packet Protocol
A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data
if write or acknowledge if read, and stop condition. The DSD1793 supports only slave receivers and slave
transmitters.
9
SDA
SCL
St
Start
17
8
18
9
18
9
Sp
Stop
Slave Address
ACK
DATA
ACK
DATA
ACK
Condition
R/W
R/W :
Read Operation if 1, Otherwise Write Operation
DATA: 8 Bits (Byte)
ACK:
Acknowledgement of a Byte if 0
NACK: Not Acknowledgement if 1
Write operation
Transmitter
M
S
M
S
M
S
…
S
M
Data Type
St
Slave address
W
ACK
DATA
ACK
DATA
ACK
…
ACK
Sp
Read operation
Transmitter
M
S
M
S
M
…
M
Data Type
St
Slave address
R
ACK
DATA
ACK
DATA
ACK
…
NACK
Sp
NOTE: M: Master device
S: Slave device
St: Start condition
Sp: Stop condition
W: Write
R: Read
Figure 28. Basic I2C Framework
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| DSD1794ADBG4 | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24B 192 kHz Stereo Audio DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
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