參數(shù)資料
型號: DSD1793DBR
元件分類: DAC
英文描述: 24 BIT 192 KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER
中文描述: 24位192千赫采樣高級分段音頻立體聲數(shù)模轉(zhuǎn)換器
文件頁數(shù): 9/47頁
文件大?。?/td> 428K
代理商: DSD1793DBR
DSD1793
SLES075A MARCH 2003 REVISED JANUARY 2004
www.ti.com
17
AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes PLRCK (pin 1), PBCK (pin 2), and PDATA (pin 3). PBCK
is the serial audio bit clock, and it is used to clock the serial data present on PDATA into the serial shift register of
the audio interface. Serial data is clocked into the DSD1793 on the rising edge of PBCK. PLRCK is the serial audio
left/right word clock.
The DSD1793 requires the synchronization of PLRCK and the system clock, but does not need a specific phase
relation between PLRCK and the system clock.
If the relationship between PLRCK and the system clock changes more than
±6 PBCK, internal operation is initialized
within 1/fS and analog outputs are forced to the bipolar zero level until resynchronization between PLRCK and the
system clock is completed.
PCM Audio Data Formats and Timing
The DSD1793 supports industry-standard audio data formats, including standard right-justified, I2S, and left-justified.
The data formats are shown in Figure 27. Data formats are selected using the format bits, FMT[2:0], in control register
18. The default data format is 24-bit I2S. All formats require binary 2s complement, MSB-first audio data. Figure 26
shows a detailed timing diagram for the serial audio interface.
PDATA
t(BCH)
1.4 V
PBCK
PLRCK
t(BCL)
t(LB)
t(BCY)
t(DS)
t(DH)
1.4 V
t(BL)
PARAMETERS
MIN
MAX
UNITS
t(BCY)
PBCK pulse cycle time
70
ns
t(BCL)
PBCK pulse duration, LOW
30
ns
t(BCH)
PBCK pulse duration, HIGH
30
ns
t(BL)
PBCK rising edge to PLRCK edge
10
ns
t(LB)
PLRCK edge to PBCK rising edge
10
ns
t(DS)
PDATA setup time
10
ns
t(DH)
PDATA hold time
10
ns
PLRCK clock data
50%
± 2 bit clocks
Figure 26. Timing of Audio Interface
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