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參數(shù)資料
| 型號： | DSM2180F390T6 |
| 廠商： | 意法半導體 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) |
| 中文描述： | 帝斯曼（數(shù)字信號處理器系統(tǒng)內(nèi)存）模擬器件公司的ADSP - 218X系列（5V電源） |
| 文件頁數(shù)： | 28/63頁 |
| 文件大?。?/td> | 809K |
| 代理商： | DSM2180F390T6 |
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DSM2180F3
28/63
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. See application
note AN1171for details on how to specify logic us-
ing PSDsoft Express.
As shown in Figure 15, the CPLD has the following
blocks:
I
16 Input Macrocells (IMC)
I
16 Output Macrocells (OMC)
I
Macrocell Allocator
I
Product Term Allocator
I
AND Array capable of generating up to 130
product terms
I
Two I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the device internal data
bus and can be directly accessed by the DSP. This
enables the DSP software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macro cell architectures.
Figure 15. Macrocell and I/O Port
Output Macrocell (OMC).
Eight of the Output
Macrocells (OMC) are connected to Port B pins
and are named as McellAB0-McellAB7. The other
eight Macrocells are connected to Ports B or C
pins and are named as McellBC0-McellBC7.
OMCs may be used for internal feedback only
(buried registers), or their outputs may be routed
to external Port pins.
The Output Macrocell (OMC) architecture is
shown in Figure 17. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the
XOR gate. The Output Macrocell (OMC) can im-
plement either sequential logic, using the flip-flop
I/O PORTS
CPLD Macrocells
Input Macrocells
LATCHED
ADDRESS OUT
MUX
M
M
M
D
D
Q
Q
Q
G
D
Q D
WR
WR
PDR
DATA
PALLOCATOR
DIR
SELECT
INPUT
Pfrom other
MacrocellS
POLARITY
PROUP TO 10
CLOCK
PR
DI LD
D/T
CK
CL
Q
SELECT
PT CLEAR
PT
GLOBAL
PT Output Enable (OE)
Macrocell Feedback
I/O Port Input
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET
MCU DATA IN
/REG
SELECT
Mato
IAlloc.
OCPLD
TO OTHER I/O PORTS
P
P
DSP ADDRESS / DATA BUS
MOut to
MCU
CDATA
A
CPLD OUTPUT
I/O Pin
AI04902B
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DSM2180F3-90T6 | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 8M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| DSM2180F3V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSM (DIGITAL SIGNAL PROCESSOR SYSTEM MEMORY) FOR ANALOG DEVICES ADSP-218X FAMILY (3.3V SUPPLY) |
| DSM2180F3V-15 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (3.3V Supply) |
| DSM2180F3V15K6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (3.3V Supply) |
| DSM2180F3V-15K6 | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 8M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
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