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參數(shù)資料
| 型號(hào)： | DSM2180F390T6 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) |
| 中文描述： | 帝斯曼（數(shù)字信號(hào)處理器系統(tǒng)內(nèi)存）模擬器件公司的ADSP - 218X系列（5V電源） |
| 文件頁(yè)數(shù)： | 8/63頁(yè) |
| 文件大?。?/td> | 809K |
| 代理商： | DSM2180F390T6 |
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DSM2180F3
8/63
Figure 5. Block Diagram
Programmable Logic (PLDs)
The DSM family contains two PLDS that may op-
tionally run in Turbo or Non-Turbo mode. PLDs op-
erate faster (less propagation delay) while in
Turbo mode but consume more power than Non-
Turbo mode. Non-Turbo mode allows the PLDs to
automatically go to standby when no inputs are
change to conserve power. The Turbo mode set-
ting is controlled at runtime by DSP software.
Decode PLD (DPLD).
This is programmable log-
ic used to select one of the eight individual Flash
memory segments or the group of control registers
within the DSM device. The DPLD can also option-
ally drive external chip select signals on Port D
pins. DPLD input signals include: DSP address
and control signals, Page Register outputs, DSM
Port Pins, CPLD logic feedback.
Complex PLD (CPLD).
This programmable logic
is used to create both combinatorial and sequen-
tial general purpose logic. The CPLD contains 16
Output Macrocells (OMCs) and 16 Input Macro-
cells (IMCs). PSD macrocell registers are unique
in that that have direct connection to the DSP data
bus allowing them to be loaded and read directly
by the DSP at runtime. This direct access is good
for making small peripheral devices (shifters,
counters, state machines, etc.) that are accessed
directly by the DSP with little overhead. DPLD in-
puts include DSP address and control signals,
Page Register outputs, DSM Port Pins, and CPLD
feedback.
OMCs: The general structure of the CPLD is simi-
lar in nature to a 22V10 PLD device with the famil-
iar sum-of-products (AND-OR) construct. True
and compliment versions of 64 input signals are
available to a large AND array. AND array outputs
feed into a multiple product-term OR gate within
each OMC (up to 10 product-terms for each
OMC). Logic output of the OR gate can be passed
on as combinatorial logic or combined with a flip-
flop within in each OMC to realize sequential logic.
OMCs can be used as a buried nodes with feed-
back to the AND array or OMC output can be rout-
ed to pins on Port B or PortC.
IMCs: Inputs from pins on Port B or Port C are
routed to IMCs for conditioning (clocking or latch-
ing) as they enter the chip, which is good for sam-
pling and debouncing inputs. Alternatively, IMCs
can pass Port input signals directly to PLD inputs
AI04911
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
I/O PORT
PC0
PC1
PC3
PC4
PC5
PC6
I/O PORT
COMPLEX PLD
(CPLD)
16 INPUT
MICRO<>CELLS
16 OUTPUT MICRO<>CELLS
A
B
B
C
A
B
B
C
A
B
B
C
A
B
B
C
A
B
B
C
A
B
B
C
A
B
B
C
A
B
B
C
PAGE REG
SECURITY
LOCK
P
ALLO-
CATOR
FLASH MEMORY
PIN FEEDBACK
NODE FEEDBACK
DSM2180F3
DSP SYSTEM
MEMORY
INTERNAL ADDR, DATA, CONTROL BUS LINKED TO DSP
DECODE PLD
(DPLD)
AND
ARRAY
EXTERNAL
CHIP SELECTS
FS0-7
JTAG-ISP
TO ALL AREAS
OF CHIP
B
B
B
B
C
C
C
C
B
C
B
C
B
C
B
C
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
PC2
PC7
DSP
ADDR
DSP
CONTROL
CNTL0
CNTL1
CNTL2
PD0
PD1
PD2
RST\
3 OPTIONAL OUTPUTS TO PORT D
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
DSP
DATA
8 SEGMENTS, 16 KB
128 KBytes TOTAL
RUNTIME CONTROL
CSIOP REGISTER FILE
CSIOP
POWER MANAGEMENT
fs0
fs7
fs6
fs5
fs4
fs3
fs2
fs1
EXTERNAL CHIP SELECTS, ESC0-2
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| DSM2180F3V15T6 | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) |
| DSM2180F3V90K6 | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSM2180F3-90T6 | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 8M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| DSM2180F3V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSM (DIGITAL SIGNAL PROCESSOR SYSTEM MEMORY) FOR ANALOG DEVICES ADSP-218X FAMILY (3.3V SUPPLY) |
| DSM2180F3V-15 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (3.3V Supply) |
| DSM2180F3V15K6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (3.3V Supply) |
| DSM2180F3V-15K6 | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 8M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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