參數(shù)資料
型號： DSM2190F4
廠商： 意法半導體
元件分類： 數(shù)字信號處理
英文描述： 16-bit fixed point DSP with Flash
中文描述： 具有閃存的 16 位定點 DSP
文件頁數(shù)： 6/61頁
文件大?。?/td> 530K
代理商： DSM2190F4
DSM2190F4
6/61
ARCHITECTURAL OVERVIEW
Major functional blocks are shown in Figure 5.
DSP Address/Data/Control Interface
These DSP signals attach directly to the DSM for
a glueless connection. An 8-bit data connection is
formed and all 22 DSP address lines can be de-
coded as well as DSP memory strobes;
BMS
,
IOMS
, and
MSx
. There are many different ways the
DSM2190F4 can be configured and used depend-
ing on system requirements. One convenient way
is to combine the function of the
MSx
signals into
the
BMS
signal. Doing this allows the DSP core to
access DSM memory at runtime even after the
boot process is complete using only the
BMS
sig-
nal. Combining
MSx
and
BMS
consumes less I/O
pin(s) on the DMS device. See Analog Devices
ADSP-2191 DSP Hardware Reference Manual,
Chapter 7, Code Example: BMS Runtime Access.
Alternatively, any of the
MSx
signals may also be
used to decode any of the sectors of DSM Main
Flash or Secondary flash memories.
Main Flash Memory
The 2M bit (256K x 8) Flash memory is divided into
eight equally-sized 32K byte sectors that are indi-
vidually selectable through the Decode PLD. Each
Flash memory sector can be located at any ad-
dress as defined by the user with PSDsoft Ex-
press. DSP code and data is easily placed in flash
memory using the PSDsoft Express software de-
velopment tool.
Secondary Flash Memory
The 256K bit (32K x 8) Flash memory is divided
into eight equally-sized 8K byte sectors that are in-
dividually selectable through the Decode PLD.
Each Flash memory sector can be located at any
address as defined by the user with PSDsoft Ex-
press. DSP code and data can also be placed
Secondary Flash memory using the PSDsoft Ex-
press development tool.
Secondary flash memory is good for storing data
because of its small sectors. Additionally, software
EEPROM emulation techniques can be used for
small data sets that change frequently on a byte-
by-byte basis.
Secondary flash may also be used to store custom
start-up code for applications that do not “boot” us-
ing DMA, but instead start executing code from ex-
ternal memory upon reset. Storing code here can
keep the entire Main Flash free of initialization
code for clean software partitioning. If only one or
more 8K byte sectors are needed for start-up
code, the remaining sectors of Secondary Flash
may be used for data storage.
Secondary Flash may also be used as an exten-
sion to Main Flash memory producing a total of
288K bytes
Miscellaneous: Main and Secondary Flash memo-
ries are totally independent, allowing concurrent
operation if needed. The DSP can read from one
memory while erasing or programming the other.
The DSP can erase Flash memories by individual
sectors or the entire Flash memory array may be
erased at one time. Each sector in either Flash
memory may be individually write protected, block-
ing any writes from the DSP (good for boot and
start-up code protection). The Flash memories au-
tomatically go to standby between DSP read or
write accesses to conserve power. Maximum ac-
cess times include sector decoding time. Maxi-
mum erase cycles is 100K and data retention is 15
years minimum. Flash memory, as well as the en-
tire DSM device may be programmed with the
JTAG ISP interface with no DSP involvement.
Programmable Logic (PLDs)
The DSM family contains two PLDS that may op-
tionally run in Turbo or Non-Turbo mode. PLDs op-
erate faster (less propagation delay) while in
Turbo mode but consume more power than Non-
Turbo mode. Non-Turbo mode allows the PLDs to
automatically go to standby when no inputs are
change to conserve power. The Turbo mode set-
ting is controlled at runtime by DSP software.
Decode PLD (DPLD).
This is programmable log-
ic used to select one of the eight individual Main
Flash memory segments, one of four individual
Secondary Flash memory segments, or the group
of control registers within the DSM device. The
DPLD can also optionally drive external chip select
signals on Port D pins. DPLD input signals include:
DSP address and control signals, Page Register
outputs, DSM Port Pins, CPLD logic feedback.
Complex PLD (CPLD).
This programmable logic
is used to create both combinatorial and sequen-
tial general purpose logic. The CPLD contains 16
Output Macrocells (OMCs) and 16 Input Macro-
cells (IMCs). PSD Macrocell registers are unique
in that that have direct connection to the DSP data
bus allowing them to be loaded and read directly
by the DSP at runtime. This direct access is good
for making small peripheral devices (shifters,
counters, state machines, etc.) that are accessed
directly by the DSP with little overhead. DPLD in-
puts include DSP address and control signals,
Page Register outputs, DSM Port Pins, and CPLD
feedback.
相關(guān)PDF資料
PDF描述
DSM2190F4V 16-bit fixed point DSP with Flash
DSM2190F4V-15K6 16-bit fixed point DSP with Flash
DSM2190F4V-15T6 16-bit fixed point DSP with Flash
DSM3MA GENERAL-USE RECTIFIER DIODE
DSP-A1092 NATURAL SOUND AV AMPLIFIRE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSM2190F4V 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply)
DSM2190F4V-15K6 功能描述:SPLD - 簡單可編程邏輯器件 3.3V 16M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
DSM2190F4V-15T6 功能描述:SPLD - 簡單可編程邏輯器件 3.3V 16M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
DSM-22LA 制造商:Tenma 功能描述:Dual Digital Satellite Meter
DSM2C250 制造商:Molex 功能描述:REED SWITCH W/NC 3P M/MP 5M
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*