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參數(shù)資料
| 型號： | DSM2190F4 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點 DSP |
| 文件頁數(shù)： | 7/61頁 |
| 文件大?。?/td> | 530K |
| 代理商： | DSM2190F4 |
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DSM2190F4
Figure 5. Block Diagram
OMCs: The general structure of the CPLD is simi-
lar in nature to a 22V10 PLD device with the famil-
iar sum-of-products (AND-OR) construct. True
and compliment versions of 64 input signals are
available to a large AND array. AND array outputs
feed into a multiple product-term OR gate within
each OMC (up to 10 product-terms for each
OMC). Logic output of the OR gate can be passed
on as combinatorial logic or combined with a flip-
flop within in each OMC to realize sequential logic.
OMCs can be used as a buried nodes with feed-
back to the AND array or OMC output can be rout-
ed to pins on Port B or PortC.
IMCs: Inputs from pins on Port B or Port C are
routed to IMCs for conditioning (clocking or latch-
ing) as they enter the chip, which is good for sam-
pling and debouncing inputs. Alternatively, IMCs
can pass Port input signals directly to PLD inputs
without clocking or latching. The DSP may read
the IMCs at any time.
Runtime Control Registers
A block of 256 bytes is decoded inside the DSM
device as DSM control and status registers. 27
registers are used in the block of 256 locations to
control the output state of I/O pins, to read I/O
pins, to control power management, to read/write
macrocells, and other functions at runtime. See
Table 4 for description. The base address of these
256 locations is referred to in this data sheet as
csiop (Chip Select I/O Port). Individual registers
within this block are accessed with an offset from
the base address. The DSP accesses csiopregis-
ters using I/O memory with the
IOMS
strobe. csiop
registers are accessed as bytes.
Memory Page Register
This 8-bit register can be loaded and read by the
DSP at runtime as one of the csiopregisters. Its
outputs feed directly into the PLDs. The page reg-
ister can be used for special memory mapping re-
quirements and also for general logic.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
I/O PORT
PC0
PC1
PC3
PC4
PC5
PC6
PC7
I/O PORT
COMPLEX PLD
(CPLD)
16 Input
Macrocell
16 Output Macrocells
A
B
B
C
A
B
B
C
A
B
B
C
A
B
B
C
A
B
B
C
A
B
B
C
A
B
B
C
A
B
B
C
PAGE REG
SECURITY
LOCK
P
ALLO-
CATOR
PIN FEEDBACK
NODE FEEDBACK
DSM2190F4
DSP SYSTEM
MEMORY
INTERNAL ADDR, DATA, CONTROL BUS LINKED TO DSP
DECODE PLD
(DPLD)
AND
ARRAY
EXTERNAL
CHIP SELECTS
JTAG-ISP
TO ALL AREAS
OF CHIP
B
B
B
B
C
C
C
C
B
C
B
C
B
C
B
C
EXTERNAL CHIP SELECTS, ESC0-2
RUNTIME CONTROL
CSIOP REGISTER FILE
POWER MANAGEMENT
CSIOP
MAIN FLASH MEMORY
8 SEGMENTS, 32 KB
256 KBytes TOTAL
fs0
fs7
2nd FLASH MEMORY
csboot3
32 KBytes TOTAL
csboot0
CSBOOT0-3
FS0-7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
PD0
PD1
PD2
DSP
ADDR
DSP
CONTROL
CNTL0
CNTL1
CNTL2
PC2
RST\
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
DSP
DATA
AI04960B
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PDF描述 |
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| DSM2190F4V | 16-bit fixed point DSP with Flash |
| DSM2190F4V-15K6 | 16-bit fixed point DSP with Flash |
| DSM2190F4V-15T6 | 16-bit fixed point DSP with Flash |
| DSM3MA | GENERAL-USE RECTIFIER DIODE |
| DSP-A1092 | NATURAL SOUND AV AMPLIFIRE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSM2190F4V | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply) |
| DSM2190F4V-15K6 | 功能描述:SPLD - 簡單可編程邏輯器件 3.3V 16M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| DSM2190F4V-15T6 | 功能描述:SPLD - 簡單可編程邏輯器件 3.3V 16M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| DSM-22LA | 制造商:Tenma 功能描述:Dual Digital Satellite Meter |
| DSM2C250 | 制造商:Molex 功能描述:REED SWITCH W/NC 3P M/MP 5M |
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