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| 型號： | DSP56311VF150 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 2/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 150MHZ 196-BGA |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 系列： | DSP56K/Symphony |
| 類型： | 定點 |
| 接口： | 主機(jī)接口，SSI，SCI |
| 時鐘速率： | 150MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 384kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
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DSP56311 Technical Data, Rev. 8
1-6
Freescale Semiconductor
Signals/Connections
BR
Output
Reset: Output
(deasserted)
State during Stop/Wait
depends on BRH bit
setting:
BRH = 0: Output,
deasserted
BRH = 1: Maintains
last state (that is, if
asserted, remains
asserted)
Bus Request—Asserted when the DSP requests bus mastership. BR is deasserted
when the DSP no longer needs the bus. BR may be asserted or deasserted
independently of whether the DSP56311 is a bus master or a bus slave. Bus
“parking” allows BR to be deasserted even though the DSP56311 is the bus master.
(See the description of bus “parking” in the BB signal description.) The bus request
hold (BRH) bit in the BCR allows BR to be asserted under software control even
though the DSP does not need the bus. BR is typically sent to an external bus
arbitrator that controls the priority, parking, and tenure of each master on the same
external bus. BR is affected only by DSP requests for the external bus, never for the
internal bus. During hardware reset, BR is deasserted and the arbitration is reset to
the bus slave state.
BG
Input
Ignored Input
Bus Grant—Asserted by an external bus arbitration circuit when the DSP56311
becomes the next bus master. When BG is asserted, the DSP56311 must wait until
BB is deasserted before taking bus mastership. When BG is deasserted, bus
mastership is typically given up at the end of the current bus cycle. This may occur in
the middle of an instruction that requires more than one external bus cycle for
execution.
The default operation of this bit requires a set-up and hold time as specified in
Chapter 2
. An alternate mode can be invoked: set the asynchronous bus arbitration
enable (ABE) bit (Bit 13) in the Operating Mode Register. When this bit is set, BG and
BB are synchronized internally. This eliminates the respective set-up and hold time
requirements but adds a required delay between the deassertion of an initial BG input
and the assertion of a subsequent BG input.
BB
Input/ Output
Ignored Input
Bus Busy—Indicates that the bus is active. Only after BB is deasserted can the
pending bus master become the bus master (and then assert the signal again). The
bus master may keep BB asserted after ceasing bus activity regardless of whether
BR is asserted or deasserted. Called “bus parking,” this allows the current bus master
to reuse the bus without rearbitration until another device requires the bus. BB is
deasserted by an “active pull-up” method (that is, BB is driven high and then released
and held high by an external pull-up resistor).
The default operation of this signal requires a set-up and hold time as specified in
Chapter 2. An alternative mode can be invoked by setting the ABE bit (Bit 13) in the
Operating Mode Register. When this bit is set, BG and BB are synchronized
internally. See BG for additional information.
Note: BB requires an external pull-up resistor.
CAS
Output
Tri-stated
Column Address Strobe—When the DSP is the bus master, CAS is an active-low
output used by DRAM to strobe the column address. Otherwise, if the Bus
Mastership Enable (BME) bit in the DRAM control register is cleared, the signal is tri-
stated.
Note: DRAM access is not supported above 100 MHz.
BCLK
Output
Tri-stated
Bus Clock
When the DSP is the bus master, BCLK is active when the ATE bit in the Operating
Mode Register is set. When BCLK is active and synchronized to CLKOUT by the
internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle.
Note: At operating frequencies above 100 MHz, this signal produces a low-amplitude
waveform that is not usable externally by other devices.
BCLK
Output
Tri-stated
Bus Clock Not
When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise,
the signal is tri-stated.
Note: At operating frequencies above 100 MHz, this signal produces a low-amplitude
waveform that is not usable externally by other devices.
Table 1-8.
External Bus Control Signals (Continued)
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description
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| DSP56311VF150B1 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSP56311VF150R2 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSP56311VF160 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC SSP26111VF160A RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSP56311VL150 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP PBFREE RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSP56311VL150B1 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP PBFREE RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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