- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19503 > DSP56311VF150 (Freescale Semiconductor)IC DSP 24BIT 150MHZ 196-BGA PDF資料下載
參數(shù)資料
| 型號： | DSP56311VF150 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 23/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 150MHZ 196-BGA |
| 標準包裝： | 126 |
| 系列： | DSP56K/Symphony |
| 類型： | 定點 |
| 接口： | 主機接口，SSI，SCI |
| 時鐘速率： | 150MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 384kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
iii
Features
Table 1 lists the features of the DSP56311 device.
Table 1. DSP56311 Features
Feature
Description
High-Performance
DSP56300 Core
Up to 150 million multiply-accumulates per second (MMACS) (300 MMACS using the EFCOP in filtering
applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O
Object code compatible with the DSP56000 core with highly parallel instruction set
Data arithmetic logic unit (Data ALU) with fully pipelined 24
× 24-bit parallel Multiplier-Accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)
test access port (TAP)
Enhanced Filter
Coprocessor (EFCOP)
Internal 24
× 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
Operation at the same frequency as the core (up to 150 MHz)
Support for a variety of filter modes, some of which are optimized for cellular base station applications:
Real finite impulse response (FIR) with real taps
Complex FIR with complex taps
Complex FIR generating pure real or pure imaginary outputs alternately
A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
Direct form 2 (DFII) IIR filter
Four scaling factors (1, 4, 8, 16) for IIR output
Adaptive FIR filter with true least mean square (LMS) coefficient updates
Adaptive FIR filter with delayed LMS coefficient updates
Internal Peripherals
Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
Serial communications interface (SCI) with baud rate generator
Triple timer module
Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
enabled
Internal Memories
192
× 24-bit bootstrap ROM
128 K
× 24-bit RAM total
Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
:
Program
RAM Size
Instruction
Cache Size
X Data RAM
Size*
Y Data RAM
Size*
Instruction
Cache
Switch
Mode
MSW1 MSW0
32 K
× 24-bit
0
48 K
× 24-bit
48 K
× 24-bit
disabled
0/1
31 K
× 24-bit 1024 × 24-bit
48 K
× 24-bit
48 K
× 24-bit
enabled
disabled
0/1
96 K
× 24-bit
0
16 K
× 24-bit
16 K
× 24-bit
disabled
enabled
0
95 K
× 24-bit 1024 × 24-bit
16 K
× 24-bit
16 K
× 24-bit
enabled
0
80 K
× 24-bit
0
24 K
× 24-bit
24 K
× 24-bit
disabled
enabled
0
1
79 K
× 24-bit 1024 × 24-bit
24 K
× 24-bit
24 K
× 24-bit
enabled
0
1
64 K
× 24-bit
0
32 K
× 24-bit
32 K
× 24-bit
disabled
enabled
1
0
63 K
× 24-bit 1024 × 24-bit
32 K
× 24-bit
32 K
× 24-bit
enabled
1
0
48 K
× 24-bit
0
40 K
× 24-bit
40 K
× 24-bit
disabled
enabled
1
47 K
× 24-bit 1024 × 24-bit
40 K
× 24-bit
40 K
× 24-bit
enabled
1
*Includes 10 K
× 24-bit shared memory (that is, memory shared by the core and the EFCOP)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GCB13DHRD | CONN CARD EXTEND 26POS .050" SLD |
| LT3083ET#TRPBF | IC REG LDO ADJ 3A TO-220-5 |
| DSP56303AG100 | IC DSP 24BIT 100MHZ 144-LQFP |
| V300A3V3E264BL3 | CONVERTER MOD DC/DC 3.3V 264W |
| KRM55WR72A156MH01K | CAP CER 15UF 100V 20% X7R 2220 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56311VF150B1 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| DSP56311VF150R2 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| DSP56311VF160 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC SSP26111VF160A RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| DSP56311VL150 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP PBFREE RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| DSP56311VL150B1 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP PBFREE RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。