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| 型號： | DSP56311VL150R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 71/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 150MHZ 196-MAPBGA |
| 標準包裝： | 1 |
| 系列： | DSP56K/Symphony |
| 類型： | 定點 |
| 接口： | 主機接口，SSI，SCI |
| 時鐘速率： | 150MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 384kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | DSP56311VL150R2CT |
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Power Consumption Considerations
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
4-3
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This
recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQC, IRQD,
TA
, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended.
Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate
capacitance. This is especially critical in systems with higher capacitive loads that could create higher
transient currents in the VCC and GND circuits.
All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins with
internal pull-up resistors (TRST, TMS, DE).
Take special care to minimize noise levels on the VCCP, GNDP, and GNDP1 pins.
The following pins must be asserted during power-up: RESET and TRST. A stable EXTAL signal should be
supplied before deassertion of RESET. If the VCC reaches the required level before EXTAL is stable or
other “required RESET duration” conditions are met (see Table 2-7), the device circuitry can be in an
uninitialized state that may result in significant power consumption and heat-up. Designs should minimize
this condition to the shortest possible duration.
Ensure that during power-up, and throughout the DSP56311 operation, VCCQH is always higher or equal to
the VCC voltage level.
If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due
to synchronous operation of the devices.
The Port A data bus (D[0–23]), HI08, ESSI0, ESSI1, SCI, and timers all use internal keepers to maintain the
last output value even when the internal signal is tri-stated. Typically, no pull-up or pull-down resistors
should be used with these signal lines. However, if the DSP is connected to a device that requires pull-up
resistors (such as an MPC8260), the recommended resistor value is 10 K
or less. If more than one DSP
must be connected in parallel to the other device, the pull-up resistor value requirement changes as
follows:
—2 DSPs = 7 K
or less
—3 DSPs = 4 K
or less
—4 DSPs = 3 K
or less
—5 DSPs = 2 K
or less
—6 DSPs = 1.5 K
or less
4.3 Power Consumption Considerations
Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption
are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is
charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by this
formula:
Equation 3:
Where:
C
=
node/pin capacitance
V
=
voltage swing
f
=
frequency of node/pin toggle
Example 4-1. Current Consumption
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33
MHz), the current consumption is expressed in Equation 4.
I
CV
f
×
=
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