參數(shù)資料
型號(hào)： DSP56321
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Digital Signal Processor
中文描述： 24位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 27/84頁(yè)
文件大小： 898K
代理商： DSP56321
AC Electrical Characteristics
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
2-7
20 Delay from RD assertion to interrupt
request deassertion for level sensitive
fast interrupts
1, 6, 7
(WS + 3.25)
×
T
C
–
10.94
—
Note 7
—
Note 7
—
Note 7
—
Note 7
ns
21 Delay from WR assertion to interrupt
request deassertion for level sensitive
fast interrupts
1, 6, 7
SRAM WS = 3
SRAM WS
≥
4
(WS + 3)
×
T
C
– 10.94
(WS + 2.5)
×
T
C
– 10.94
—
—
Note 7
Note 7
—
—
Note 7
Note 7
—
—
Note 7
Note 7
—
—
Note 7
Note 7
ns
ns
24 Duration for IRQA assertion to recover
from Stop state
8.0
—
8.0
—
8.0
—
8.0
—
ns
25 Delay from IRQA assertion to fetch of
first instruction (when exiting Stop)
2, 3
DPLL is not active during Stop
(PCTL Bit 1 = 0) and Stop delay is
enabled (Operating Mode Register
Bit 6 = 0)
DPLL is not active during Stop
(PCTL Bit 1 = 0) and Stop delay is
not enabled (Operating Mode
Register Bit 6 = 1)
DPLL is active during Stop (PCTL
Bit 1 = 1; Implies No Stop Delay)
DPLT + (128K
×
T
C
)
DPLT + (23.75 ± 0.5)
×
T
C
(10.0
±
1.75)
×
T
C
662.2
μ
s
6.9
41.25
209.9
ms
188.8
58.8
662.2
μ
s
6.9
37.5
209.9
ms
188.8
53.3
662.2
μ
s
6.9
34.4
209.9
ms
188.8
49.0
662.2
μ
s
6.9
30.0
209.9
ms
188.8
43.0
—
μ
s
ns
26 Duration of level sensitive IRQA
assertion to ensure interrupt service
(when exiting Stop)
2, 3
DPLL is not active during Stop
(PCTL bit 1 = 0) and Stop delay is
enabled (Operating Mode Register
Bit 6 = 0)
DPLL is not active during Stop
(PCTL bit 1 = 0) and Stop delay is
not enabled (Operating Mode
Register Bit 6 = 1)
DPLL is active during Stop ((PCTL
bit 1 = 0; implies no Stop delay)
DPLT + (128 K
×
T
C
)
DPLT + (20.5
±
0.5)
×
T
C
5.5
×
T
C
805.4
150.1
27.5
—
—
—
805.4
150.1
25
—
—
—
805.4
150.1
22.9
—
—
—
805.4
150.1
20.0
—
—
—
μ
s
μ
s
ns
27 Interrupt Request Rate
HI08, ESSI, SCI, Timer
DMA
IRQ, NMI (edge trigger)
IRQ, NMI (level trigger)
12T
C
8T
C
8T
C
12T
C
—
—
—
—
60.0
40.0
40.0
60.0
—
—
—
—
54.6
36.4
36.4
54.6
—
—
—
—
50.0
33.4
33.4
50.0
—
—
—
—
43.7
29.2
29.2
43.7
ns
ns
ns
ns
28 DMA Request Rate
Data read from HI08, ESSI, SCI
Data write to HI08, ESSI, SCI
Timer
IRQ, NMI (edge trigger)
6T
C
7T
C
2T
C
3T
C
—
—
—
—
30.0
35.0
10.0
15.0
—
—
—
—
27.3
31.9
9.1
13.7
—
—
—
—
25.0
29.2
8.3
12.5
—
—
—
—
21.84
25.48
7.28
10.92
ns
ns
ns
ns
29 Delay from IRQA, IRQB, IRQC, IRQD,
NMI assertion to external memory
(DMA source) access address out
valid
4.25
×
T
C
+ 2.0
23.25
—
21.34
—
19.72
—
17.45
—
ns
Table 2-7.
Reset, Stop, Mode Select, and Interrupt Timing
5
(CONTINUED)
No.
Characteristics
Expression
200 MHz
220 MHz
240 MHz
275 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
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