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參數(shù)資料
| 型號： | DSP56321 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-Bit Digital Signal Processor |
| 中文描述： | 24位數(shù)字信號處理器 |
| 文件頁數(shù)： | 44/84頁 |
| 文件大?。?/td> | 898K |
| 代理商： | DSP56321 |
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DSP56321 Technical Data, Rev. 11
2-24
Freescale Semiconductor
Specifications
451 TXC rising edge to FST out (word-
length) low
—
—
12.5
8.3
—
—
12.5
8.3
—
—
12.5
8.3
—
—
12.5
8.3
x ck
i ck
ns
452 TXC rising edge to data out enable from
high impedance
—
—
12.5
8.3
—
—
12.5
8.3
—
—
12.5
8.3
—
—
12.5
8.3
x ck
i ck
ns
453 TXC rising edge to Transmitter 0 drive
enable assertion
—
—
12.5
13.5
—
—
12.5
13.5
—
—
12.5
13.5
—
—
12.5
13.5
x ck
i ck
ns
454 TXC rising edge to data out valid
—
—
12.5
8.3
—
—
12.5
8.3
—
—
12.5
8.3
—
—
12.5
8.3
x ck
i ck
ns
455 TXC rising edge to data out high
impedance
3
—
—
30.0
8.3
—
—
30.0
8.3
—
—
30.0
8.3
—
—
30.0
8.3
x ck
i ck
ns
456 TXC rising edge to Transmitter 0 drive
enable deassertion
3
—
—
12.5
8.3
—
—
12.5
8.3
—
—
12.5
8.3
—
—
12.5
8.3
x ck
i ck
ns
457 FST input (bl, wr) setup time before
TXC falling edge
2
5.0
10.0
—
—
5.0
10.0
—
—
5.0
10.0
—
—
5.0
10.0
—
—
x ck
i ck
ns
458 FST input (wl) to data out enable from
high impedance
—
—
15.0
8.0
—
—
15.0
8.0
—
—
15.0
8.0
—
—
15.0
8.0
x ck
i ck
ns
459 FST input (wl) to Transmitter 0 drive
enable assertion
—
—
15.0
18.0
—
—
15.0
18.0
—
—
15.0
18.0
—
—
15.0
18.0
x ck
i ck
ns
460 FST input (wl) setup time before TXC
falling edge
5.0
10.0
—
—
5.0
10.0
—
—
5.0
10.0
—
—
5.0
10.0
—
—
x ck
i ck
ns
461 FST input hold time after TXC falling
edge
3.8
5.0
—
—
3.8
5.0
—
—
3.8
5.0
—
—
3.8
5.0
—
—
x ck
i ck
ns
462 Flag output valid after TXC rising edge
—
—
12.5
8.3
—
—
12.5
8.3
—
—
12.5
8.3
—
—
12.5
8.3
x ck
i ck
ns
Notes:
1.
For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in
Table 2-5
on page 2-4) and the
ESSI control register. T
ECCX
must be
≥
T
C
×
3, in accordance with the note below Table 7-1 in the DSP56321 Reference
Manual. T
ECCI
must be
≥
T
C
×
4, in accordance with the explanation of CRA[PSR] and the ESSI Clock Generator Functional
Block Diagram shown in
Figure 7-3
of the DSP56321 Reference Manual.
The word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform, but
spreads from one serial clock before the first bit clock (same as the Bit Length Frame Sync signal) until the one before last bit
clock of the first word in the frame.
Periodically sampled and not 100 percent tested
V
CCQH
= 3.3 V
±
0.3 V, V
CCQL
= 1.6 V
±
0.1 V; T
J
=
0°C to +85°C, C
L
= 50 pF
TXC (SCK Pin) = Transmit Clock
RXC (SC0 or SCK Pin) = Receive Clock
FST (SC2 Pin) = Transmit Frame Sync
FSR (SC1 or SC2 Pin) Receive Frame Sync
i ck = Internal Clock; x ck = External Clock
i ck a = Internal Clock, Asynchronous Mode (asynchronous implies that TXC and RXC are two different clocks)
i ck s = Internal Clock, Synchronous Mode (synchronous implies that TXC and RXC are the same clock)
In the timing diagrams below, the clocks and frame sync signals are drawn using the clock falling edge as a the first reference.
Clock and frame sync polarities are programmable in Control Register B (CRB). Refer to the DSP56321 Reference Manualfor
details.
2.
3.
4.
5.
6.
7.
Table 2-12.
ESSI Timings (Continued)
No.
Characteristics
4, 6
Symbol
Expression
200 MHz
220 MHz
240 MHz
275 MHz
Cond-
ition
5
Unit
Min Max Min Max Min Max Min Max
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