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參數(shù)資料
| 型號： | DSP56321VL275 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-Bit Digital Signal Processor |
| 中文描述： | 24位數(shù)字信號處理器 |
| 文件頁數(shù)： | 26/84頁 |
| 文件大小： | 898K |
| 代理商： | DSP56321VL275 |
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DSP56321 Technical Data, Rev. 11
2-6
Freescale Semiconductor
Specifications
2.4.4
Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7.
Reset, Stop, Mode Select, and Interrupt Timing
5
Notes:
1.
2.
3.
4.
5.
6.
Refer to the DSP56321 User’s Manualfor a detailed description of register reset values.
The total multiplication factor (MF) includes both integer and fractional parts (that is, MF = MFI + MFN/MFD).
The numerator (MFN) should be less than the denominator (MFD).
DPLL lock procedure duration is specified for the case when an external clock source is supplied to the EXTAL pin.
Frequency-only Lock Mode or non-integer MF, after partial reset.
Frequency and Phase Lock Mode, integer MF, after full reset.
No.
Characteristics
Expression
200 MHz
220 MHz
240 MHz
275 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
8
Delay from RESET assertion to all
pins at reset value
3
—
—
26
—
26
—
26
—
26
ns
9
Required RESET duration
4
Power on, external clock
generator, DPLL disabled
Power on, external clock
generator, DPLL enabled
Power on, internal oscillator
During STOP, XTAL disabled
During STOP, XTAL enabled
During normal operation
50
×
ET
C
1000
×
ET
C
75000
×
ET
C
75000
×
ET
C
2.5
×
T
C
2.5
×
T
C
250.0
5.0
0.375
0.375
12.5
17
—
—
—
—
—
—
227.5
4.55
0.341
0.341
11.38
16
—
—
—
—
—
—
208.5
4.17
0.313
0.313
10.43
15
—
—
—
—
—
—
182.0
3.64
0.273
0.273
9.1
9.1
—
—
—
—
—
—
ns
μ
s
ms
ms
ns
ns
10 Delay from asynchronous RESET
deassertion to first external address
output (internal reset deassertion)
Minimum
Maximum
3.25
×
T
C
+ 2.0
18.25
—
—
180
16.77
—
—
163
15.55
—
—
150
13.82
—
—
140
ns
ns
13 Mode select setup time
30.0
—
30.0
—
30.0
—
30.0
—
ns
14 Mode select hold time
0.0
—
0.0
—
0.0
—
0.0
—
ns
15 Minimum edge-triggered interrupt
request assertion width
4.0
—
4.0
—
4.0
—
4.0
—
ns
16 Minimum edge-triggered interrupt
request deassertion width
4.0
—
4.0
—
4.0
—
4.0
—
ns
17 Delay from IRQA, IRQB, IRQC, IRQD,
NMI assertion to external memory
access address out valid
Caused by first interrupt instruction
fetch
Caused by first interrupt instruction
execution
4.25
×
T
C
+ 2.0
7.25
×
T
C
+ 2.0
23.25
38.25
—
—
21.24
34.99
—
—
19.72
32.23
—
—
17.45
28.36
—
—
ns
ns
18 Delay from IRQA, IRQB, IRQC, IRQD,
NMI assertion to general-purpose
transfer output valid caused by first
interrupt instruction execution
8.9
×
T
C
44.5
—
40.45
—
37.0
—
32.37
—
ns
19 Delay from address output valid
caused by first interrupt instruction
execute to interrupt request
deassertion for level sensitive fast
interrupts
1, 6, 7
(WS + 3.75)
×
T
C
–
10.94
—
Note 7
—
Note 7
—
Note 7
—
Note 7
ns
Table 2-6.
CLKGEN and DPLL Characteristics (Continued)
Characteristics
Symbol
200 MHz
220 MHz
240 MHz
275 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
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