參數(shù)資料
型號(hào)： DSP56366P
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 56/110頁(yè)
文件大?。?/td> 1273K
代理商： DSP56366P
DSP56366 Technical Data, Rev. 3.1
3-30
Freescale Semiconductor
174
CAS assertion to column address not valid
t
CAH
5.25
×
T
C
4.0
48.5
—
ns
175
RAS assertion to column address not valid
t
AR
7.75
×
T
C
4.0
73.5
—
ns
176
Column address valid to RAS deassertion
t
RAL
6
×
T
C
4.0
56.0
—
ns
177
WR deassertion to CAS assertion
t
RCS
3.0
×
T
C
4.0
26.0
—
ns
178
CAS deassertion to WR
5
assertion
t
RCH
1.75
×
T
C
4.0
13.5
—
ns
179
RAS deassertion to WR
5
assertion
t
RRH
0.25
×
T
C
2.0
0.5
—
ns
180
CAS assertion to WR deassertion
t
WCH
5
×
T
C
4.2
45.8
—
ns
181
RAS assertion to WR deassertion
t
WCR
7.5
×
T
C
4.2
70.8
—
ns
182
WR assertion pulse width
t
WP
11.5
×
T
C
4.5
110.5
—
ns
183
WR assertion to RAS deassertion
t
RWL
11.75
×
T
C
4.3
113.2
—
ns
184
WR assertion to CAS deassertion
t
CWL
10.25
×
T
C
4.3
103.2
—
ns
185
Data valid to CAS assertion (write)
t
DS
5.75
×
T
C
4.0
53.5
—
ns
186
CAS assertion to data not valid (write)
t
DH
5.25
×
T
C
4.0
48.5
—
ns
187
RAS assertion to data not valid (write)
t
DHR
7.75
×
T
C
4.0
73.5
—
ns
188
WR assertion to CAS assertion
t
WCS
6.5
×
T
C
4.3
60.7
—
ns
189
CAS assertion to RAS assertion (refresh)
t
CSR
1.5
×
T
C
4.0
11.0
—
ns
190
RAS deassertion to CAS assertion (refresh)
t
RPC
2.75
×
T
C
4.0
23.5
—
ns
191
RD assertion to RAS deassertion
t
ROH
11.5
×
T
C
4.0
111.0
—
ns
192
RD assertion to data valid
t
GA
10
×
T
C
7.0
—
93.0
ns
193
RD deassertion to data not valid
3
t
GZ
0.0
—
ns
194
WR assertion to data active
0.75
×
T
C
0.3
7.2
—
ns
195
WR deassertion to data high impedance
0.25
×
T
C
—
2.5
ns
1
The number of wait states for out-of-page access is specified in the DCR.
2
The refresh period is specified in the DCR.
3
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
OFF
and not t
GZ
.
4
The asynchronous delays specified in the expressions are valid for DSP56366.
5
Either t
RCH
or t
RRH
must be satisfied for read cycles.
Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States
1, 2
(continued)
No.
Characteristics
3
Symbol
Expression
4
Min
Max
Unit
相關(guān)PDF資料
PDF描述
DSP56366UM 24-Bit Audio Digital Signal Processor
DSP56367P 24-Bit Audio Digital Signal Processor
DSP56367UM 24-Bit Audio Digital Signal Processor
DSP56600 Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
DSP56852E 16-bit Digital Signal Controllers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56366UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
DSP56367P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56371 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device
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