參數(shù)資料
型號: DSP56854FGE
廠商: Freescale Semiconductor
文件頁數(shù): 15/60頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 120MHZ 128-LQFP
標(biāo)準(zhǔn)包裝: 72
系列: 568xx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 120MHz
連通性: EBI/EMI,SCI,SPI,SSI
外圍設(shè)備: DMA,POR,WDT
輸入/輸出數(shù): 41
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: SRAM
RAM 容量: 16K x 16
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.98 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 128-LQFP
包裝: 托盤
56854 Technical Data, Rev. 6
22
Freescale Semiconductor
50
TRST
Input
Test Reset (TRST)—As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted whenever RESET is
asserted. The only exception occurs in a debugging environment,
since the Enhanced OnCE/JTAG module is under the control of the
debugger. In this case it is not necessary to assert TRST when
asserting RESET . Outside of a debugging environment RESET
should be permanently asserted by grounding the signal, thus
disabling the Enhanced OnCE/JTAG module on the device.
Note:
For normal operation, connect TRST directly to VSS. If the
design is to be used in a debugging environment, TRST may be tied to VSS
through a 1K resistor.
49
DE
Input/Output
Debug Event (DE)—This is an open-drain, bidirectional, active low
signal. As an input, it is a means of entering debug mode of
operation from an external command controller. As an output, it is a
means of acknowledging that the chip has entered debug mode.
This pin is connected internally to a weak pull-up resistor.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
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