參數(shù)資料
型號(hào): DSP56855BU120
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù): 20/52頁(yè)
文件大?。?/td> 618K
代理商: DSP56855BU120
56855 Technical Data, Rev. 6
20
Freescale Semiconductor
4.2 DC Electrical Characteristics
Table 4-4 DC Electrical Characteristics
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
50pF, f
op
= 120MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Input high voltage (XTAL/EXTAL)
V
IHC
V
DDA
– 0.8
V
DDA
V
DDA
+ 0.3
V
Input low voltage (XTAL/EXTAL)
V
ILC
-0.3
0.5
V
Input high voltage
V
IH
2.0
5.5
V
Input low voltage
V
IL
-0.3
0.8
V
Input current low (pullups disabled)
I
IL
-1
1
μ
A
Input current high (pullups disabled)
I
IH
-1
1
μ
A
Output tri-state current low
I
OZL
-10
10
μ
A
Output tri-state current high
I
OZH
-10
10
μ
A
Output High Voltage
V
OH
V
DDIO
– 0.7
V
Output Low Voltage
V
OL
0.4
V
Output High Current
I
OH
8
16
mA
Output Low Current
I
OL
8
16
mA
Input capacitance
C
IN
8
pF
Output capacitance
C
OUT
12
pF
V
DD
supply current (Core logic, memories, peripherals)
Run
1
Deep Stop
2
Light Stop
3
1.
2.
3.
4.
Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.
Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating.
Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating.
I
DD
includes current for core logic, internal memories, and all internal peripheral logic circuitry.
I
DD4
70
0.05
5
110
10
14
mA
mA
mA
V
DDIO
supply current (I/O circuity)
Run
5
Deep Stop
2
I
DDIO
40
0
50
1.5
mA
mA
V
DDA
supply current (analog circuity)
Deep Stop
2
I
DDA
60
120
μ
A
Low Voltage Interrupt
6
V
EI
2.5
2.85
V
Low Voltage Interrupt Recovery Hysteresis
V
EIH
50
mV
Power on Reset
7
POR
1.5
2.0
V
Note:
no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out.
Run (operating) I
DD
measured using external square wave clock source (f
osc
= 4MHz) into XTAL. All inputs 0.2V from rail;
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