參數(shù)資料
型號: DSP56855BU120
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 39/52頁
文件大?。?/td> 618K
代理商: DSP56855BU120
Enhanced Synchronous Serial Interface (ESSI) Timing
56855 Technical Data, Rev. 6
Freescale Semiconductor
39
Figure 4-25 Slave Mode Clock Timing
3.
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have
been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables
and in the figures.
All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
4.
50 percent duty cycle
5.
bl = bit length; wl = word length
t
THS
t
TSS
t
HS
t
SS
t
RFSWLS
t
RFSWHS
t
RFBLS
t
RFSBHS
t
TXHIS
t
TXNVS
t
FTXVS
t
TXVS
t
TXES
t
FTXES
t
TFSWLS
t
TFSWHS
t
TFSBLS
t
TFSBHS
t
SCKL
t
SCKW
t
SCKH
First Bit
Last Bit
SCK input
SC2 (bl) input
SC2 (wl) input
STD
SC0 input
SC1 (bl) input
SC1 (wl) input
SRD
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