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參數(shù)資料
| 型號(hào)： | DSP56858FV120 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號(hào)控制器 |
| 文件頁數(shù)： | 21/64頁 |
| 文件大小： | 956K |
| 代理商： | DSP56858FV120 |
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Introduction
56858 Technical Data, Rev. 6
Freescale Semiconductor
21
TCK
L8
60
Input
Test Clock Input (TCK)
—This input pin provides a gated clock to
synchronize the test logic and to shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
TDI
K7
58
Input
Test Data Input (TDI)
—This input pin provides a serial input data
stream to the JTAG/OnCE port. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
TDO
G6
57
Output(Z)
Test Data Output (TDO)
—This tri-statable output pin provides a serial
output data stream from the JTAG/Enhanced OnCE port. It is driven in
the Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.
TMS
J7
59
Input
Test Mode Select Input (TMS)
—This input pin is used to sequence
the JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
TRST
L7
56
Input
Test Reset (TRST)
—As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete hardware
reset, TRST should be asserted whenever RESET is asserted. The
only exception occurs in a debugging environment, since the
Enhanced OnCE/JTAG module is under the control of the debugger. In
this case it is not necessary to assert TRST when asserting RESET.
Outside of a debugging environment RESET should be permanently
asserted by grounding the signal, thus disabling the Enhanced
OnCE/JTAG module on the device.
Note:
to be used in a debugging environment, TRST may be tied to V
SS
through a
1K resistor.
For normal operation, connect TRST directly to V
SS
. If the design is
Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal
Name
BGA
Pin No.
LQFP
Pin No.
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56858FVE | 16-bit Digital Signal Controllers |
| DSP56858VF120 | 16-bit Digital Signal Controllers |
| DSP5685XEVMUM | Feature Phone Software Application Product Brief |
| DSP5685XUM | Feature Phone Software Application Product Brief |
| DSP56F800ERM | Feature Phone Software Application Product Brief |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56858FVE | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 120Mhz/120MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSP56858PB_D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56858 Digital Signal Processor Product Brief |
| DSP56858VF120 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 120Mhz/120MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| DSP5685XEVMUM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Feature Phone Software Application Product Brief |
| DSP5685XSFPPB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Feature Phone Software Application |
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