參數(shù)資料
型號(hào): DSP56858FV120
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù): 34/64頁(yè)
文件大小: 956K
代理商: DSP56858FV120
56858 Technical Data, Rev. 6
34
Freescale Semiconductor
Figure 4-11 Asynchronous Reset Timing
Figure 4-12 External Interrupt Timing (Negative-Edge-Sensitive)
Figure 4-13 External Level-Sensitive Interrupt Timing
7.
Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,
recovery will take an extra cycle (to restart the clock), and t
clk
will resume at the input clock source rate.
ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.
8.
First Fetch
A0–Axx,
D0–D15
CS,
RD, WR
RESET
First Fetch
t
RDA
t
RA
t
RAZ
IRQA
IRQB
t
IRW
A0–Axx,
CS,
RD
,
WR
IRQA,
IRQB
First Interrupt Instruction Execution
a) First Interrupt Instruction Execution
Purpose
I/O Pin
IRQA,
IRQB
b) General Purpose I/O
t
IG
t
IDM
General
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