參數(shù)資料
型號: DSP56F802TA60E
廠商: Freescale Semiconductor
文件頁數(shù): 15/40頁
文件大?。?/td> 0K
描述: IC DSP 60MHZ 16KB FLASH 32-LQFP
標準包裝: 250
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 60MHz
連通性: SCI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 20KB(10K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-LQFP
包裝: 托盤
56F802 Technical Data, Rev. 9
22
Freescale Semiconductor
Figure 3-6 Flash Mass Erase Cycle
3.5 Clock Operation
The 56F802 device clock is derived from an on-chip relaxation oscillator. The internal PLL generates a
master reference frequency that determines the speed at which chip operations occur.
The PRECS bit in the PLLCR (phase-locked loop control register) word (bit 2) must be set to 0 for internal
oscillator use.
3.5.1
Use of On-Chip Relaxation Oscillator
The 56F802 internal relaxation oscillator provides the chip clock without the need for an external crystal
or ceramic resonator. The frequency output of this internal oscillator can be corrected by adjusting the 8-bit
IOSCTL (internal oscillator control) register. Each bit added or deleted changes the output frequency of
the oscillator allowing incremental adjustment until the desired frequency is achieved. Figures 9 and 10
show the typical characteristics of the 56F802 relaxation oscillator with respect to temperature and trim
value.
During factory production test, an oscillator calibration procedure is executed which determines an
optimum trim value for a given device (8MHz at 25oC). This optimum trim value is then stored at address
$103F in the Data Flash Information Block and recalled during a trim routine in the boot sequence
(executed after power-up and RESET). This trim routine automatically sets the oscillator frequency by
programming the IOSCTL register with the optimum trim value.
XADR
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1
Trcv
Tme
MAS1
IFREN
XE
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