Ensure that capacitor leads and associated printed circuit traces that conn" />
參數(shù)資料
型號: DSP56F802TA60E
廠商: Freescale Semiconductor
文件頁數(shù): 30/40頁
文件大?。?/td> 0K
描述: IC DSP 60MHZ 16KB FLASH 32-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 60MHz
連通性: SCI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 20KB(10K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-LQFP
包裝: 托盤
56F802 Technical Data, Rev. 9
36
Freescale Semiconductor
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)
pins are less than 0.5 inch per capacitor lead.
Bypass the VDD and VSS layers of the PCB with approximately 100 μF, preferably with ceramic or tantalum
capacitors which tend to provide better performance tolerances.
Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and GND circuits.
Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs
that do not require debugging functionality, such as consumer products, TRST should be tied low.
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an
interface to this port to allow in-circuit Flash programming.
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